README: update

README

@@ -39,10 +39,8 @@ by generating the verilog rtl that you will use as a standard core.
 -------------------------
 - add standardized interfaces (AXI, Avalon-ST)
 - add DMA interface to MAC
-- add hardware ARP table
-- add hardware IP layer
-- add hardware UDP layer
 - add hardware Etherbone support
+- add RGMII/SGMII PHYs
 - ... See below Support and Consulting :)
 
 If you want to support these features, please contact us at florent [AT]
@@ -52,13 +50,50 @@ devel [AT] lists.m-labs.hk.
 
 [> Getting started
 ------------------
-  XXX
+1. Install Python3 and Xilinx's Vivado software
+
+2. Obtain Migen and install it:
+  git clone https://github.com/m-labs/migen
+  cd migen
+  python3 setup.py install
+  cd ..
+
+3. Obtain LiteScope and install it:
+  git clone https://github.com/enjoy-digital/litescope
+  cd litescope
+  python3 setup.py install
+  cd ..
+
+4. Obtain MiSoC:
+  git clone https://github.com/m-labs/misoc --recursive
+  XXX add setup.py to MiSoC for external use of misoclib?
+
+5. Obtain LiteEth
+  git clone https://github.com/enjoy-digital/liteeth
+
+6. Build and load UDP loopback design (only for KC705 for now):
+  python3 make.py all (-s UDPSoCDevel to add LiteScopeLA)
+
+7. Test design (only for KC705 for now):
+  go to ./test directory and run:
+  change com port in config.py to your com port
+  try to ping 192.168.1.40
+  python3 test_udp.py
 
 [> Simulations:
-  XXX
+  Simulations are available in ./liteth/test/:
+    - mac_core_tb
+    - mac_wishbone_tb
+    - arp_tb
+    - ip_tb
+    - icmp_tb
+    - udp_tb
+  All ethernet layers have their own model tested against real Ethernet dumps (dumps.py)
+  To run a simulation, move to ./liteeth/test and run:
+    make simulation_name
 
 [> Tests :
-  XXX
+  An UDP loopback is provided and be controlled with: /test/test_udp.py
 
 [> License
 -----------