soc/cores/prbs: minor cosmetic cleanups.
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@ -59,16 +59,16 @@ class PRBSTX(Module):
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config = Signal(2)
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# generators
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# Generators
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self.specials += MultiReg(self.config, config)
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prbs7 = PRBS7Generator(width)
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prbs15 = PRBS15Generator(width)
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prbs31 = PRBS31Generator(width)
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self.submodules += prbs7, prbs15, prbs31
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# select
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# PRBS Selection
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prbs_data = Signal(width)
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self.comb += \
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self.comb += [
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If(config == 0b11,
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prbs_data.eq(prbs31.o)
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).Elif(config == 0b10,
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@ -76,20 +76,22 @@ class PRBSTX(Module):
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).Else(
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prbs_data.eq(prbs7.o)
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)
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]
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# optional bits reversing
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# Optional bits reversing
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if reverse:
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new_prbs_data = Signal(width)
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self.comb += new_prbs_data.eq(prbs_data[::-1])
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prbs_data = new_prbs_data
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# prbs / data mux
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self.comb += \
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# PRBS / Data Selection
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self.comb += [
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If(config == 0,
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self.o.eq(self.i)
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).Else(
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self.o.eq(prbs_data)
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)
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]
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# PRBS Checkers ------------------------------------------------------------------------------------
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@ -129,22 +131,22 @@ class PRBS31Checker(PRBSChecker):
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class PRBSRX(Module):
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def __init__(self, width, reverse=False):
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self.i = Signal(width)
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self.config = Signal(2)
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self.i = Signal(width)
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self.errors = Signal(32)
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# # #
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config = Signal(2)
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# optional bits reversing
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# Optional bits reversing
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prbs_data = self.i
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if reverse:
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new_prbs_data = Signal(width)
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self.comb += new_prbs_data.eq(prbs_data[::-1])
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prbs_data = new_prbs_data
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# checkers
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# Checkers
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self.specials += MultiReg(self.config, config)
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prbs7 = PRBS7Checker(width)
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prbs15 = PRBS15Checker(width)
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@ -156,8 +158,8 @@ class PRBSRX(Module):
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prbs31.i.eq(prbs_data)
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]
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# errors count
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self.sync += \
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# Errors count
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self.sync += [
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If(config == 0,
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self.errors.eq(0)
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).Elif(self.errors != (2**32-1),
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@ -169,3 +171,4 @@ class PRBSRX(Module):
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self.errors.eq(self.errors + (prbs31.errors != 0))
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)
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)
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]
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