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migen.fhdl.size: verify fslice for negative values

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Robert Jordens 2013-12-02 19:32:13 -07:00 committed by Sebastien Bourdeauducq
parent c71eb5778f
commit 86ba9c8bbc
2 changed files with 12 additions and 5 deletions
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14
migen/fhdl/size.py
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@ -161,16 +161,20 @@ def fslice(v, s):
Examples Examples
-------- --------
>>> fslice(Signal(2), 1) #doctest: +ELLIPSIS >>> fslice(f.Signal(2), 1) #doctest: +ELLIPSIS
<migen.fhdl.structure._Slice object at 0x...> <migen.fhdl.structure._Slice object at 0x...>
>>> bin(fslice(0b1101, slice(1, None, 2))) >>> bin(fslice(0b1101, slice(1, None, 2)))
'0b10' '0b10'
>>> fslice(-1, slice(0, 4))
1
>>> fslice(-7, slice(None))
9
""" """
if isinstance(v, (bool, int)): if isinstance(v, (bool, int)):
if isinstance(s, int): if isinstance(s, int):
s = slice(s) s = slice(s)
idx = range(*s.indices(flen(v))) idx = range(*s.indices(bits_for(v)))
return sum(((v>>i) & 1) << j for j, i in enumerate(idx)) return sum(((v >> i) & 1) << j for j, i in enumerate(idx))
elif isinstance(v, f.Value): elif isinstance(v, f.Value):
return v[s] return v[s]
else: else:
@ -190,8 +194,8 @@ def freversed(v):
Examples Examples
-------- --------
>>> freversed(Signal(2)) #doctest: +ELLIPSIS >>> freversed(f.Signal(2)) #doctest: +ELLIPSIS
<migen.fhdl.structure._Slice object at 0x...> <migen.fhdl.structure.Cat object at 0x...>
>>> bin(freversed(0b1011)) >>> bin(freversed(0b1011))
'0b1101' '0b1101'
""" """

3
migen/test/test_size.py
View file

@ -32,6 +32,9 @@ class SignalSizeCase(unittest.TestCase):
fslice(self.s, sl) fslice(self.s, sl)
self.assertEqual(fslice(self.i, sl), 15) self.assertEqual(fslice(self.i, sl), 15)
self.assertEqual(fslice(self.j, sl), 8) self.assertEqual(fslice(self.j, sl), 8)
self.assertEqual(fslice(-1, 9), 1)
self.assertEqual(fslice(-1, slice(0, 4)), 0b1)
self.assertEqual(fslice(-7, slice(0, None, 1)), 0b1001)
def test_fslice_type(self): def test_fslice_type(self):
self.assertRaises(TypeError, fslice, [], 3) self.assertRaises(TypeError, fslice, [], 3)