interconnect/wishbonebridge: refresh/simplify.
This should also improve Wishbone timings.
Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash
With the following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))
errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))
# # #
wb.close()
This commit is contained in:
Florent Kermarrec
parent
c136113a9b
commit
873d95e517
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@ -1,167 +1,127 @@
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# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from math import log2
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from migen import *
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from migen.genlib.misc import chooser, WaitTimer
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from migen.genlib.record import Record
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import WaitTimer
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import stream
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# Wishbone Streaming Bridge ------------------------------------------------------------------------
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CMD_WRITE = 0x01
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CMD_READ = 0x02
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class WishboneStreamingBridge(Module):
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cmds = {
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"write": 0x01,
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"read": 0x02
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}
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def __init__(self, phy, clk_freq):
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def __init__(self, phy, clk_freq, data_width=32, address_width=32):
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self.wishbone = wishbone.Interface()
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self.comb += phy.source.ready.eq(1) # Always accept incoming stream.
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# # #
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byte_counter = Signal(3, reset_less=True)
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byte_counter_reset = Signal()
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byte_counter_ce = Signal()
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self.sync += \
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If(byte_counter_reset,
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byte_counter.eq(0)
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).Elif(byte_counter_ce,
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byte_counter.eq(byte_counter + 1)
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)
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cmd = Signal(8, reset_less=True)
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length = Signal(8, reset_less=True)
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address = Signal(address_width, reset_less=True)
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data = Signal(data_width, reset_less=True)
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bytes_count = Signal(int(log2(data_width//8)), reset_less=True)
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words_count = Signal(8, reset_less=True)
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word_counter = Signal(3, reset_less=True)
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word_counter_reset = Signal()
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word_counter_ce = Signal()
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self.sync += \
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If(word_counter_reset,
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word_counter.eq(0)
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).Elif(word_counter_ce,
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word_counter.eq(word_counter + 1)
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)
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bytes_count_done = (bytes_count == (data_width//8 - 1))
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words_count_done = (words_count == (length - 1))
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cmd = Signal(8, reset_less=True)
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cmd_ce = Signal()
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length = Signal(8, reset_less=True)
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length_ce = Signal()
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address = Signal(32, reset_less=True)
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address_ce = Signal()
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data = Signal(32, reset_less=True)
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rx_data_ce = Signal()
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tx_data_ce = Signal()
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self.sync += [
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If(cmd_ce, cmd.eq(phy.source.data)),
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If(length_ce, length.eq(phy.source.data)),
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If(address_ce, address.eq(Cat(phy.source.data, address[0:24]))),
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If(rx_data_ce,
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data.eq(Cat(phy.source.data, data[0:24]))
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).Elif(tx_data_ce,
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data.eq(self.wishbone.dat_r)
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)
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]
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fsm = ResetInserter()(FSM(reset_state="IDLE"))
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timer = WaitTimer(int(clk_freq//10))
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fsm = ResetInserter()(FSM(reset_state="RECEIVE-CMD"))
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timer = WaitTimer(int(100e-3*clk_freq))
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self.comb += timer.wait.eq(~fsm.ongoing("RECEIVE-CMD"))
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self.submodules += fsm, timer
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self.comb += [
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fsm.reset.eq(timer.done),
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phy.source.ready.eq(1)
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]
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fsm.act("IDLE",
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self.comb += fsm.reset.eq(timer.done)
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fsm.act("RECEIVE-CMD",
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NextValue(bytes_count, 0),
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NextValue(words_count, 0),
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If(phy.source.valid,
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cmd_ce.eq(1),
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If((phy.source.data == self.cmds["write"]) |
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(phy.source.data == self.cmds["read"]),
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NextState("RECEIVE_LENGTH")
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),
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byte_counter_reset.eq(1),
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word_counter_reset.eq(1)
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NextValue(cmd, phy.source.data),
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NextState("RECEIVE-LENGTH")
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)
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)
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fsm.act("RECEIVE_LENGTH",
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fsm.act("RECEIVE-LENGTH",
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If(phy.source.valid,
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length_ce.eq(1),
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NextState("RECEIVE_ADDRESS")
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NextValue(length, phy.source.data),
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NextState("RECEIVE-ADDRESS")
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)
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)
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fsm.act("RECEIVE_ADDRESS",
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fsm.act("RECEIVE-ADDRESS",
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If(phy.source.valid,
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address_ce.eq(1),
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byte_counter_ce.eq(1),
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If(byte_counter == 3,
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If(cmd == self.cmds["write"],
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NextState("RECEIVE_DATA")
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).Elif(cmd == self.cmds["read"],
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NextState("READ_DATA")
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),
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byte_counter_reset.eq(1),
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)
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)
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)
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fsm.act("RECEIVE_DATA",
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If(phy.source.valid,
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rx_data_ce.eq(1),
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byte_counter_ce.eq(1),
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If(byte_counter == 3,
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NextState("WRITE_DATA"),
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byte_counter_reset.eq(1)
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)
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)
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)
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self.comb += [
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self.wishbone.adr.eq(address + word_counter),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**len(self.wishbone.sel) - 1)
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]
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fsm.act("WRITE_DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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word_counter_ce.eq(1),
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If(word_counter == (length-1),
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NextState("IDLE")
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).Else(
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NextState("RECEIVE_DATA")
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)
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)
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)
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fsm.act("READ_DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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tx_data_ce.eq(1),
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NextState("SEND_DATA")
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)
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)
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self.comb += \
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chooser(data, byte_counter, phy.sink.data, n=4, reverse=True)
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fsm.act("SEND_DATA",
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phy.sink.valid.eq(1),
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If(phy.sink.ready,
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byte_counter_ce.eq(1),
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If(byte_counter == 3,
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word_counter_ce.eq(1),
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If(word_counter == (length-1),
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NextState("IDLE")
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NextValue(address, Cat(phy.source.data, address)),
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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If(cmd == CMD_WRITE,
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NextState("RECEIVE-DATA")
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).Elif(cmd == CMD_READ,
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NextState("READ-DATA")
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).Else(
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NextState("READ_DATA"),
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byte_counter_reset.eq(1)
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NextState("RECEIVE-CMD")
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)
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)
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)
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)
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self.comb += timer.wait.eq(~fsm.ongoing("IDLE"))
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self.comb += phy.sink.last.eq((byte_counter == 3) & (word_counter == length - 1))
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fsm.act("RECEIVE-DATA",
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If(phy.source.valid,
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NextValue(data, Cat(phy.source.data, data)),
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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NextState("WRITE-DATA")
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)
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)
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)
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self.comb += [
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self.wishbone.adr.eq(address),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**(data_width//8) - 1)
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]
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fsm.act("WRITE-DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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NextValue(words_count, words_count + 1),
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NextValue(address, address + 1),
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If(words_count_done,
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NextState("RECEIVE-CMD")
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).Else(
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NextState("RECEIVE-DATA")
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)
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)
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)
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fsm.act("READ-DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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NextValue(data, self.wishbone.dat_r),
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NextState("SEND-DATA")
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)
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)
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cases = {}
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for i, n in enumerate(reversed(range(data_width//8))):
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cases[i] = phy.sink.data.eq(data[8*n:])
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self.comb += Case(bytes_count, cases)
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fsm.act("SEND-DATA",
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phy.sink.valid.eq(1),
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If(phy.sink.ready,
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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NextValue(words_count, words_count + 1),
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NextValue(address, address + 1),
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If(words_count_done,
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NextState("RECEIVE-CMD")
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).Else(
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NextState("READ-DATA")
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)
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)
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)
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)
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self.comb += phy.sink.last.eq(bytes_count_done & words_count_done)
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if hasattr(phy.sink, "length"):
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self.comb += phy.sink.length.eq(4*length)
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self.comb += phy.sink.length.eq((data_width//8)*length)
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