clocking: clean up and add comments
This commit is contained in:
Florent Kermarrec
parent
387cf90cf8
commit
879478a6e4
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@ -8,7 +8,7 @@ from lib.sata.k7sataphy.clocking import K7SATAPHYClocking
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from lib.sata.k7sataphy.ctrl import K7SATAPHYHostCtrl, K7SATAPHYDeviceCtrl
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class K7SATAPHY(Module):
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def __init__(self, pads, host=True):
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def __init__(self, pads, clk_freq, host=True,):
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self.sink = Sink([("d", 32)], True)
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self.source = Source([("d", 32)], True)
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@ -17,7 +17,7 @@ class K7SATAPHY(Module):
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gtx.rxrate.eq(0b000),
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gtx.txrate.eq(0b000),
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]
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clocking = K7SATAPHYClocking(pads, gtx)
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clocking = K7SATAPHYClocking(pads, gtx, clk_freq)
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rxalign = K7SATAPHYRXAlign()
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rxconvert = K7SATAPHYRXConvert()
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txconvert = K7SATAPHYTXConvert()
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@ -1,3 +1,5 @@
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from math import ceil
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from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.fsm import FSM, NextState
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@ -23,15 +25,19 @@ class K7SATAPHYReconfig(Module):
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)
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class K7SATAPHYClocking(Module):
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def __init__(self, pads, gtx):
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def __init__(self, pads, gtx, clk_freq):
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self.reset = Signal()
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self.gtx_reset = Signal()
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self.clock_domains.cd_sata = ClockDomain()
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self.clock_domains.cd_sata_tx = ClockDomain()
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self.clock_domains.cd_sata_rx = ClockDomain()
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# TX clocking
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# CPLL
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# (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps
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# (SATA2 & SATA1) VCO still @ 3 GHz, Line rate is decreased with output divivers.
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# When changing rate, reconfiguration of the CPLL over DRP is needed to:
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# - update the output divider
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# - update the equalizer configuration (specific for each line rate).
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refclk = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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@ -41,6 +47,11 @@ class K7SATAPHYClocking(Module):
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)
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self.comb += gtx.gtrefclk0.eq(refclk)
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# TX clocking
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# (SATA3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits), sata clk @ 150MHz (32-bits)
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# (SATA2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits), sata clk @ 75MHz (32-bits)
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# (SATA1) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 75MHz (16-bits), sata clk @ 37.5MHz (32-bits)
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# When changing rate, reconfiguration of the MMCM is needed to update the output divider.
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mmcm_reset = Signal()
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mmcm_locked = Signal()
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mmcm_drp = DRPBus()
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@ -49,7 +60,7 @@ class K7SATAPHYClocking(Module):
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mmcm_clk0_o = Signal()
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mmcm_clk1_o = Signal()
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self.specials += [
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Instance("BUFG", i_I=refclk, o_O=mmcm_clk_i),
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Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i),
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Instance("MMCME2_ADV",
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p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked,
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@ -59,14 +70,14 @@ class K7SATAPHYClocking(Module):
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=6.666,
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p_CLKFBOUT_MULT_F=8.000, p_CLKFBOUT_PHASE=0.000, p_DIVCLK_DIVIDE=2,
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p_CLKFBOUT_MULT_F=8.000, p_CLKFBOUT_PHASE=0.000, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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# CLK0
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p_CLKOUT0_DIVIDE_F=2.000, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
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p_CLKOUT0_DIVIDE_F=4.000, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
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# CLK1
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p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o,
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p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o,
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),
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Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
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Instance("BUFG", i_I=mmcm_clk1_o, o_O=self.cd_sata.clk),
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@ -77,8 +88,11 @@ class K7SATAPHYClocking(Module):
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]
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# RX clocking
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# (SATA3) sata_rx recovered clk @ 300MHz from CPLL RXOUTCLK
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# (SATA2) sata_rx recovered clk @ 150MHz from CPLL RXOUTCLK
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# (SATA1) sata_rx recovered clk @ 150MHz from CPLL RXOUTCLK
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self.specials += [
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Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_rx.clk),
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Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
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]
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self.comb += [
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gtx.rxusrclk.eq(self.cd_sata_rx.clk),
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@ -94,6 +108,26 @@ class K7SATAPHYClocking(Module):
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gtx.txphinit.eq(0)
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]
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# RX buffer bypass logic
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self.comb += [
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gtx.rxphdlyreset.eq(0),
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gtx.rxdlyen.eq(0),
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gtx.rxphalign.eq(0),
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gtx.rxphalignen.eq(0),
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]
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# Configuration Reset
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# After configuration, GTX resets can not be asserted for 500ns
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# See AR43482
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reset_en = Signal()
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clk_period_ns = 1000000000/clk_freq
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reset_en_cnt_max = ceil(500/clk_period_ns)
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reset_en_cnt = Signal(max=reset_en_cnt_max, reset=reset_en_cnt_max-1)
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self.sync += If(~reset_en, reset_en_cnt.eq(reset_en_cnt-1))
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self.comb += reset_en.eq(reset_en_cnt == 0)
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# once channel TX is reseted, reset TX buffer
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txbuffer_reseted = Signal()
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self.sync += \
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@ -106,29 +140,10 @@ class K7SATAPHYClocking(Module):
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)
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)
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# RX buffer bypass logic
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self.comb += [
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gtx.rxphdlyreset.eq(0),
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gtx.rxdlyen.eq(0),
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gtx.rxphalign.eq(0),
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gtx.rxphalignen.eq(0),
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]
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# wait till CDR is locked
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# cdr_cnt = Signal(14, reset=0b10011100010000)
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cdr_cnt = Signal(14, reset=1024)
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cdr_locked = Signal()
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self.sync += \
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If(cdr_cnt != 0,
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cdr_cnt.eq(cdr_cnt - 1)
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).Else(
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cdr_locked.eq(1)
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)
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# once CDR is locked and channel RX reseted, reset RX buffer
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# once channel RX is reseted, reset RX buffer
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rxbuffer_reseted = Signal()
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self.sync += \
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If(cdr_locked & gtx.rxresetdone,
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If(gtx.rxresetdone,
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If(~rxbuffer_reseted,
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gtx.rxdlysreset.eq(1),
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rxbuffer_reseted.eq(1)
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@ -152,11 +167,11 @@ class K7SATAPHYClocking(Module):
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gtx.rxuserrdy.eq(gtx.cplllock),
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gtx.txuserrdy.eq(gtx.cplllock),
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# TX
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gtx.gttxreset.eq(rst_cnt_done & (self.reset | self.gtx_reset | ~gtx.cplllock )),
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gtx.gttxreset.eq(reset_en & (self.reset | ~gtx.cplllock)),
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# RX
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gtx.gtrxreset.eq(rst_cnt_done & (self.reset | self.gtx_reset | ~gtx.cplllock)),
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gtx.gtrxreset.eq(reset_en & (self.reset | ~gtx.cplllock)),
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# PLL
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gtx.cpllreset.eq(rst_cnt_done & (self.reset | ~cdr_locked))
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gtx.cpllreset.eq(self.reset | ~reset_en)
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]
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# SATA TX/RX clock domains
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self.specials += [
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@ -94,7 +94,7 @@ class TestDesign(UART2WB):
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UART2WB.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), host=True)
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self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), host=False)
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self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True)
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self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
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default_subtarget = TestDesign
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