Merge branch 'master' into dev/litex-sim-gmii-xgmii

.github/workflows/ci.yml

@@ -16,6 +16,7 @@ jobs:
           sudo apt-get install wget build-essential python3
           pip3 install setuptools
           pip3 install requests
+          pip3 install meson
 
       # Install (n)Migen / LiteX / Cores
       - name: Install LiteX

.gitignore

@@ -91,3 +91,6 @@ ENV/
 
 # Rope project settings
 .ropeproject
+
+# VS Code settings
+.vscode

CHANGES

@@ -1,14 +1,72 @@
-[> 2021.XX, planned for August 2021
------------------------------------
+[> 2021.08, released on September 15th 2021
+-------------------------------------------
 
 	[> Issues resolved
 	------------------
 	- wishbone/UpConverter: Fix SEL propagation.
+	- cores/i2s:            Fix SYNC sampling.
+	- BIOS/lib*:            Fix GCC warnings.
+	- cpu/software:         Fix stack alignment issues.
+	- cpu/blackparrot:      Fix integration.
+	- interconnect/axi:     Fix valid signal in connect_to_pads for axi lite.
+	- software/hw/common:   Fix _csr_rd_buf/_csr_wr_buf for sizeof(buf[0]) < CSR_DW_BYTES case.
+	- software/soc.h:       Fix interoperability with assembly.
+	- interconnect/stream:  Fix n=1 case on Multiplexer/Demultiplexer.
+	- interconnect/axi:     Fix BURST_WRAP case on AXIBurst2Beat.
+	- cpu/VexRiscv-SMP:     Fix build without a memory bus.
+	- cpu/software:         Fix CLANG detection.
+	- build/software:       Force a fresh software build when cpu-type/variant is changed.
+	- cores/uart:           Fix TX reset level.
+	- BIOS:                 Fix PHDR link error.
+	- BIOS:                 Fix build-id link error.
+	- LiteDRAM:             Fix Artix7/DDR3 calibraiton at low speed.
 
 	[> Added Features
 	-----------------
-	- cpu/vexriscv:   Add CFU support.
-	- soc/controller: Add separate SoC/CPU reset fields.
+	- cores/video:               Add 7-Series HDMI PHY over GTPs.
+	- cores/jtagbone:            Allow JTAG chain selection.
+	- programmer:                Add iCESugar programmer.
+	- cpu/vexriscv:              Add CFU support.
+	- soc/controller:            Add separate SoC/CPU reset fields.
+	- BIOS/liblitedram:          Add debug capabilities, minor improvements.
+	- cpu/femtoRV:               Add initial FemtoRV support.
+	- cores/uart:                Cleaned-up, Add optional TX-Flush.
+	- cores/usb_ohci:            Add initial SpinalHDL's USB OHCI support (integrated in Linux-on-LiteX-Vexriscv).
+	- stream:                    Add Gate Module.
+	- soc/builder:               Allow linking external software packages.
+	- soc/software:              Allow registering init functions.
+	- cores/ram:                 Add init support to Nexus LRAM.
+	- cores/spi:                 Add Manual CS Mode for bulk transfers.
+	- cores/VexRiscv-SMP:        Make [ID]TLB size configurable.
+	- dts:                       Add GPIO IRQ support.
+	- programmer/DFUProg:        Allow to specify alt interace and to not reboot.
+	- cores/clock/ecp5:          Add dynamic phase adjustment signals.
+	- tools/litex_sim:           Mode SDRAM settings to LiteDRAM's DFI model.
+	- build/gowin:               Add AsyncResetSynchronizer/DDRInput/DDROutput implementations.
+	- build/gowin:               Add On-Chip-Oscillator support.
+	- build/gowin:               Add initial timing constraints support.
+	- build/attr_translate:      Simplify/Cleanup.
+	- programmer/OpenFPGALoader: Add cable and freq options.
+	- interconnect/packet:       Improve PacketFIFO to handle payload/param separately.
+	- clock/ecp5:                Add 4-output support.
+	- LiteSPI:                   Simplified/Cleaned-up, new MMAP architecture, applied to LiteX-Boards.
+	- soc:                       Add LiteSPI integration code.
+	- LitePCIe:                  DMA/Controller Simplified/Cleaned-up.
+	- soc/add_cpu:               Add memory mapping overrides to build log and make an exception for the CPUNone case.
+	- programmer:                Add ECPprogProgrammer.
+	- soc/software:              Add Random access option to memtest.
+	- tools:                     Add Renode generator script.
+	- tools:                     Add Zephyr DTS generator script.
+	- build/io:                  Add DDRTristate.
+	- cpu/VexRiscv:              Restructure config flags for dcache/icache presence.
+	- litex_sim:                 Improve RAM/SDRAM integration and make it closer to LiteX-Boards targets.
+	- build/sim:                 Add ODDR/IDDR/DDRSTristate simulation models.
+	- litex_sim:                 Add SPIFlash support.
+	- LiteSPI:                   Add DDR support and integration in LiteX (rate=1:1, 1:2).
+	- build/Vivado:              Make pre_synthesis/placement/routing commands similar to platform_commands.
+	- LiteDRAM:                  Refactor C code generator.
+	- LiteDRAM:                  Improve LPDDR4 support.
+	- LiteDRAM:                  Reduce ECC granularity.
 
 	[> API changes/Deprecation
 	--------------------------

litex/build/gowin/common.py

@@ -65,10 +65,42 @@ class GowinDDROutput:
     def lower(dr):
         return GowinDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
 
+# Gowin Differential Input -------------------------------------------------------------------------
+
+class GowinDifferentialInputImpl(Module):
+    def __init__(self, i_p, i_n, o):
+        self.specials += Instance("TLVDS_IBUF",
+            i_I  = i_p,
+            i_IB = i_n,
+            o_O  = o,
+        )
+
+class GowinDifferentialInput:
+    @staticmethod
+    def lower(dr):
+        return GowinDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
+
+# Gowin Differential Output -------------------------------------------------------------------------
+
+class GowinDifferentialOutputImpl(Module):
+    def __init__(self, i, o_p, o_n):
+        self.specials += Instance("TLVDS_OBUF",
+            i_I  = i,
+            o_O  = o_p,
+            o_OB = o_n,
+        )
+
+class GowinDifferentialOutput:
+    @staticmethod
+    def lower(dr):
+        return GowinDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
+
 # Gowin Special Overrides --------------------------------------------------------------------------
 
 gowin_special_overrides = {
     AsyncResetSynchronizer: GowinAsyncResetSynchronizer,
     DDRInput:               GowinDDRInput,
     DDROutput:              GowinDDROutput,
-}
+    DifferentialInput:      GowinDifferentialInput,
+    DifferentialOutput:     GowinDifferentialOutput,
+}

litex/build/gowin/gowin.py

@@ -89,6 +89,27 @@ class GowinToolchain:
         self.options = {}
         self.clocks  = dict()
 
+    def apply_hyperram_integration_hack(self, v_file):
+        # FIXME: Gowin EDA expects a very specific HypeRAM integration pattern, modify generated verilog to match it.
+
+        # Convert to vectors.
+        tools.replace_in_file(v_file, "O_hpram_reset_n", "O_hpram_reset_n[0]")
+        tools.replace_in_file(v_file, "O_hpram_cs_n",    "O_hpram_cs_n[0]")
+        tools.replace_in_file(v_file, "O_hpram_rwds",    "O_hpram_rwds[0]")
+        tools.replace_in_file(v_file, "O_hpram_ck ",     "O_hpram_ck[0] ")
+        tools.replace_in_file(v_file, "O_hpram_ck_n ",   "O_hpram_ck_n[0] ")
+        tools.replace_in_file(v_file, "O_hpram_ck,",     "O_hpram_ck[0],")
+        tools.replace_in_file(v_file, "O_hpram_ck_n,",   "O_hpram_ck_n[0],")
+        tools.replace_in_file(v_file, "wire O_hpram_reset_n[0]", "wire [0:0] O_hpram_reset_n")
+        tools.replace_in_file(v_file, "wire O_hpram_cs_n[0]",    "wire [0:0] O_hpram_cs_n")
+        tools.replace_in_file(v_file, "wire IO_hpram_rwds[0]",   "wire [0:0] IO_hpram_rwds")
+        tools.replace_in_file(v_file, "wire O_hpram_ck[0]",      "wire [0:0] O_hpram_ck")
+        tools.replace_in_file(v_file, "wire O_hpram_ck_n[0]",    "wire [0:0] O_hpram_ck_n")
+
+        # Apply Synthesis directives.
+        tools.replace_in_file(v_file, "wire [0:0] IO_hpram_rwds,", "wire [0:0] IO_hpram_rwds, /* synthesis syn_tristate = 1 */")
+        tools.replace_in_file(v_file, "wire [7:0] IO_hpram_dq,",    "wire [7:0] IO_hpram_dq,  /* synthesis syn_tristate = 1 */")
+
     def build(self, platform, fragment,
         build_dir  = "build",
         build_name = "top",
@@ -99,8 +120,8 @@ class GowinToolchain:
         cwd = os.getcwd()
         os.makedirs(build_dir, exist_ok=True)
         os.chdir(build_dir)
-
         # Finalize design
+
         if not isinstance(fragment, _Fragment):
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
@@ -111,6 +132,7 @@ class GowinToolchain:
         v_file = build_name + ".v"
         v_output.write(v_file)
         platform.add_source(v_file)
+        self.apply_hyperram_integration_hack(v_file)
 
         if platform.verilog_include_paths:
             self.options["include_path"] = "{" + ";".join(platform.verilog_include_paths) + "}"

litex/build/io.py

@@ -145,6 +145,44 @@ class DDROutput(Special):
     def lower(dr):
         raise NotImplementedError("Attempted to use a DDR output, but platform does not support them")
 
+# DDR Tristate -------------------------------------------------------------------------------------
+
+class InferedDDRTristate(Module):
+    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
+        _o  = Signal()
+        _oe = Signal()
+        _i  = Signal()
+        self.specials += DDROutput(o1, o2, _o, clk)
+        self.specials += DDROutput(oe1, oe2, _oe, clk)
+        self.specials += DDRInput(_i, i1, i2, clk)
+        self.specials += Tristate(io, _o, _oe, _i)
+
+class DDRTristate(Special):
+    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk=ClockSignal()):
+        Special.__init__(self)
+        self.io  = io
+        self.o1  = o1
+        self.o2  = o2
+        self.oe1 = oe1
+        self.oe2 = oe2
+        self.i1  = i1
+        self.i2  = i2
+        self.clk = clk
+
+    def iter_expressions(self):
+        yield self, "io",  SPECIAL_INOUT
+        yield self, "o1",  SPECIAL_INPUT
+        yield self, "o2",  SPECIAL_INPUT
+        yield self, "oe1", SPECIAL_INPUT
+        yield self, "oe2", SPECIAL_INPUT
+        yield self, "i1",  SPECIAL_OUTPUT
+        yield self, "i2",  SPECIAL_OUTPUT
+        yield self, "clk", SPECIAL_INPUT
+
+    @staticmethod
+    def lower(dr):
+        return InferedDDRTristate(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk)
+
 # Clock Reset Generator ----------------------------------------------------------------------------
 
 class CRG(Module):

litex/build/lattice/common.py

@@ -241,6 +241,31 @@ class LatticeNXSDROutput:
     def lower(dr):
         return LatticeNXSDROutputImpl(dr.i, dr.o, dr.clk)
 
+# NX SDR Input and Output via regular flip-flops ---------------------------------------------------
+
+# This is a workaround for IO-specific primitives IFD1P3BX / OFD1P3BX being unsupported in nextpnr:
+# https://github.com/YosysHQ/nextpnr/issues/698
+
+class LatticeNXSDRFFImpl(Module):
+    def __init__(self, i, o, clk):
+        self.specials += Instance("FD1P3BX",
+            i_CK = clk,
+            i_PD   = 0,
+            i_SP   = 1,
+            i_D    = i,
+            o_Q    = o,
+        )
+
+class LatticeNXSDRInputViaFlipFlop:
+    @staticmethod
+    def lower(dr):
+        return LatticeNXSDRFFImpl(dr.i, dr.o, dr.clk)
+
+class LatticeNXSDROutputViaFlipFlop:
+    @staticmethod
+    def lower(dr):
+        return LatticeNXSDRFFImpl(dr.i, dr.o, dr.clk)
+
 # NX DDR Input -------------------------------------------------------------------------------------
 
 class LatticeNXDDRInputImpl(Module):
@@ -273,6 +298,24 @@ class LatticeNXDDROutput:
     def lower(dr):
         return LatticeNXDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
 
+# NX DDR Tristate ------------------------------------------------------------------------------------
+
+class LatticeNXDDRTristateImpl(Module):
+    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
+        _o  = Signal()
+        _oe = Signal()
+        _i  = Signal()
+        self.specials += DDROutput(o1, o2, _o, clk)
+        self.specials += SDROutput(oe1 | oe2, _oe, clk)
+        self.specials += DDRInput(_i, i1, i2, clk)
+        self.specials += Tristate(io, _o, _oe, _i)
+        _oe.attr.add("syn_useioff")
+
+class LatticeNXDDRTristate:
+    @staticmethod
+    def lower(dr):
+        return LatticeNXDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk)
+
 # NX Special Overrides -----------------------------------------------------------------------------
 
 lattice_NX_special_overrides = {
@@ -281,8 +324,15 @@ lattice_NX_special_overrides = {
     SDROutput:              LatticeNXSDROutput,
     DDRInput:               LatticeNXDDRInput,
     DDROutput:              LatticeNXDDROutput,
+    DDRTristate:            LatticeNXDDRTristate,
 }
 
+lattice_NX_special_overrides_for_oxide = dict(lattice_NX_special_overrides)
+lattice_NX_special_overrides_for_oxide.update({
+    SDRInput:               LatticeNXSDRInputViaFlipFlop,
+    SDROutput:              LatticeNXSDROutputViaFlipFlop,
+})
+
 # iCE40 AsyncResetSynchronizer ---------------------------------------------------------------------
 
 class LatticeiCE40AsyncResetSynchronizerImpl(Module):

litex/build/lattice/oxide.py

@@ -108,9 +108,10 @@ def _run_script(script):
 class LatticeOxideToolchain:
     attr_translate = {
         "keep": ("keep", "true"),
+        "syn_useioff": ("syn_useioff", 1),
     }
 
-    special_overrides = common.lattice_NX_special_overrides
+    special_overrides = common.lattice_NX_special_overrides_for_oxide
 
     def __init__(self):
         self.yosys_template   = _yosys_template

litex/build/lattice/programmer.py

@@ -185,3 +185,18 @@ class EcpDapProgrammer(GenericProgrammer):
             "--freq", str(self.frequency_khz),
             bitstream_file
         ])
+
+# EcpprogProgrammer -------------------------------------------------------------------------------
+
+class EcpprogProgrammer(GenericProgrammer):
+    """ecpprog allows you to program ECP5 FPGAs and attached SPI flash using FTDI based JTAG probes
+
+    You can get `ecpprog` here: https://github.com/gregdavill/ecpprog
+    """
+    needs_bitreverse = False
+
+    def flash(self, address, bitstream_file):
+        self.call(["ecpprog", "-o", str(address), bitstream_file])
+
+    def load_bitstream(self, bitstream_file):
+        self.call(["ecpprog", "-S", bitstream_file])

litex/build/openfpgaloader.py

@@ -25,8 +25,10 @@ class OpenFPGALoader(GenericProgrammer):
         self.cmd += ["--bitstream", bitstream_file]
         self.call(self.cmd)
 
-    def flash(self, address, data_file):
+    def flash(self, address, data_file, external=False):
         self.cmd += ["--write-flash", "--bitstream", data_file]
+        if external:
+            self.cmd += ["--external-flash"]
         if address:
             self.cmd.append("--offset")
             self.cmd.append(address)

litex/build/sim/common.py

@@ -1 +1,43 @@
-sim_special_overrides = {}
+from migen import *
+from migen.fhdl.specials import Special
+
+from litex.build.io import *
+
+# DDROutput ----------------------------------------------------------------------------------------
+
+class SimDDROutputImpl(Module):
+    def __init__(self, o, i1, i2, clk):
+        self.specials += Instance("DDR_OUTPUT",
+            i_i1  = i1,
+            i_i2  = i2,
+            o_o   = o,
+            i_clk = clk
+        )
+
+class SimDDROutput:
+    @staticmethod
+    def lower(dr):
+        return SimDDROutputImpl(dr.o, dr.i1, dr.i2, dr.clk)
+
+# DDRInput -----------------------------------------------------------------------------------------
+
+class SimDDRInputImpl(Module):
+    def __init__(self, i, o1, o2, clk):
+        self.specials += Instance("DDR_INPUT",
+            o_o1  = o1,
+            o_o2  = o2,
+            i_i   = i,
+            i_clk = clk
+        )
+
+class SimDDRInput:
+    @staticmethod
+    def lower(dr):
+        return SimDDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk)
+
+# Special Overrides --------------------------------------------------------------------------------
+
+sim_special_overrides = {
+    DDROutput: SimDDROutput,
+    DDRInput:  SimDDRInput,
+}

litex/build/sim/verilog/iddr_verilog.v

@@ -0,0 +1,24 @@
+module DDR_INPUT(
+ output reg o1,
+ output reg o2,
+ input i,
+ input clk);
+
+reg _o1, _o2;
+
+always @ (posedge clk)
+  begin
+   o1 = _o1;
+   o2 = _o2;
+  end
+
+always @ (posedge clk)
+    begin
+        _o1 = i;
+    end
+
+always @ (negedge clk)
+    begin
+        _o2 = i;
+    end
+endmodule

litex/build/sim/verilog/oddr_verilog.v

@@ -0,0 +1,19 @@
+module DDR_OUTPUT(
+    input i1,
+    input i2,
+    output o,
+    input clk);
+
+wire _o;
+reg _i1, _i2;
+
+assign o = _o;
+assign _o = (clk) ? _i1 : _i2;
+
+always @ (posedge clk)
+    begin
+        _i1 = i1;
+        _i2 = i2;
+    end
+
+endmodule

litex/build/xilinx/common.py

@@ -152,6 +152,28 @@ class XilinxSDRTristate:
     def lower(dr):
         return XilinxSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
 
+# Common DDRTristate -------------------------------------------------------------------------------
+
+class XilinxDDRTristateImpl(Module):
+    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
+        _o    = Signal()
+        _oe_n = Signal()
+        _i    = Signal()
+        self.specials += DDROutput(o1, o2, _o, clk)
+        self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk)
+        self.specials += DDRInput(_i, i1, i2, clk)
+        self.specials += Instance("IOBUF",
+            io_IO = io,
+            o_O   = _i,
+            i_I   = _o,
+            i_T   = _oe_n,
+        )
+
+class XilinxDDRTristate:
+    @staticmethod
+    def lower(dr):
+        return XilinxDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk)
+
 # Common Special Overrides -------------------------------------------------------------------------
 
 xilinx_special_overrides = {
@@ -160,6 +182,7 @@ xilinx_special_overrides = {
     DifferentialInput:      XilinxDifferentialInput,
     DifferentialOutput:     XilinxDifferentialOutput,
     SDRTristate:            XilinxSDRTristate,
+    DDRTristate:            XilinxDDRTristate,
 }
 
 # Spartan6 DDROutput -------------------------------------------------------------------------------
@@ -343,18 +366,36 @@ class XilinxDDRInputUS:
 
 # Ultrascale SDROutput -----------------------------------------------------------------------------
 
+class XilinxSDROutputImplUS(Module):
+    def __init__(self, i, o, clk):
+        self.specials += Instance("FDCE",
+            i_C   = clk,
+            i_CE  = 1,
+            i_CLR = 0,
+            i_D   = i,
+            o_Q   = o
+        )
+
 class XilinxSDROutputUS:
     @staticmethod
     def lower(dr):
-        return XilinxDDROutputImplUS(dr.i, dr.i, dr.o, dr.clk)
-
-
+        return XilinxSDROutputImplUS(dr.i, dr.o, dr.clk)
+        
 # Ultrascale SDRInput ------------------------------------------------------------------------------
+class XilinxSDRInputImplUS(Module):
+    def __init__(self, i, o, clk): 
+        self.specials += Instance("FDCE",
+            i_C   = clk,
+            i_CE  = 1,
+            i_CLR = 0,
+            i_D   = i,
+            o_Q   = o
+        )
 
 class XilinxSDRInputUS:
     @staticmethod
     def lower(dr):
-        return XilinxDDRInputImplUS(dr.i, dr.o, Signal(), dr.clk)
+        return XilinxSDRInputImplUS(dr.i, dr.o, dr.clk)
 
 # Ultrascale Specials Overrides --------------------------------------------------------------------
 

litex/build/xilinx/vivado.py

@@ -102,6 +102,22 @@ def _run_script(script):
 
 # XilinxVivadoToolchain ----------------------------------------------------------------------------
 
+class XilinxVivadoCommands(list):
+    def add(self, command, **signals):
+        self.append((command, signals))
+
+    def resolve(self, vns):
+        named_commands = []
+        for command in self:
+            if isinstance(command, str):
+                named_commands.append(command)
+            else:
+                template, args = command
+                name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items())
+                named_commands.append(template.format(**name_dict))
+        return named_commands
+
+
 class XilinxVivadoToolchain:
     attr_translate = {
         "keep":            ("dont_touch", "true"),
@@ -116,9 +132,9 @@ class XilinxVivadoToolchain:
     def __init__(self):
         self.bitstream_commands                   = []
         self.additional_commands                  = []
-        self.pre_synthesis_commands               = []
-        self.pre_placement_commands               = []
-        self.pre_routing_commands                 = []
+        self.pre_synthesis_commands               = XilinxVivadoCommands()
+        self.pre_placement_commands               = XilinxVivadoCommands()
+        self.pre_routing_commands                 = XilinxVivadoCommands()
         self.incremental_implementation           = False
         self.vivado_synth_directive               = "default"
         self.opt_directive                        = "default"
@@ -129,7 +145,7 @@ class XilinxVivadoToolchain:
         self.clocks      = dict()
         self.false_paths = set()
 
-    def _build_tcl(self, platform, build_name, synth_mode, enable_xpm):
+    def _build_tcl(self, platform, build_name, synth_mode, enable_xpm, vns):
         assert synth_mode in ["vivado", "yosys"]
         tcl = []
 
@@ -191,7 +207,7 @@ class XilinxVivadoToolchain:
 
         # Add pre-synthesis commands
         tcl.append("\n# Add pre-synthesis commands\n")
-        tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
+        tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands.resolve(vns))
 
         # Synthesis
         if synth_mode == "vivado":
@@ -223,7 +239,7 @@ class XilinxVivadoToolchain:
 
         # Add pre-placement commands
         tcl.append("\n# Add pre-placement commands\n")
-        tcl.extend(c.format(build_name=build_name) for c in self.pre_placement_commands)
+        tcl.extend(c.format(build_name=build_name) for c in self.pre_placement_commands.resolve(vns))
 
         # Placement
         tcl.append("\n# Placement\n")
@@ -239,7 +255,7 @@ class XilinxVivadoToolchain:
 
         # Add pre-routing commands
         tcl.append("\n# Add pre-routing commands\n")
-        tcl.extend(c.format(build_name=build_name) for c in self.pre_routing_commands)
+        tcl.extend(c.format(build_name=build_name) for c in self.pre_routing_commands.resolve(vns))
 
         # Routing
         tcl.append("\n# Routing\n")
@@ -341,7 +357,8 @@ class XilinxVivadoToolchain:
             platform   = platform,
             build_name = build_name,
             synth_mode = synth_mode,
-            enable_xpm = enable_xpm
+            enable_xpm = enable_xpm,
+            vns        = v_output.ns,
         )
 
         # Generate design constraints (.xdc)

litex/soc/cores/clock/gowin_gw1nsr.py

@@ -0,0 +1,131 @@
+#
+# This file is part of LiteX.
+#
+# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex.soc.cores.clock.common import *
+
+class Open(Signal): pass
+
+# GoWin / GW1NSRPLL --------------------------------------------------------------------------------
+
+class GW1NSRPLL(Module):
+    nclkouts_max   = 1
+    pfd_freq_range = (  3e6,  500e6)
+    vco_freq_range = (400e6, 1000e6)
+    def __init__(self, device, vco_margin=0):
+        self.logger = logging.getLogger("GW1NPLL")
+        self.logger.info("Creating GW1NPLL.".format())
+        self.device     = device
+        self.vco_margin = vco_margin
+        self.reset      = Signal()
+        self.locked     = Signal()
+        self.clkin_freq = None
+        self.vcxo_freq  = None
+        self.nclkouts   = 0
+        self.clkouts    = {}
+        self.config     = {}
+        self.params     = {}
+
+    def register_clkin(self, clkin, freq):
+        self.clkin = Signal()
+        if isinstance(clkin, (Signal, ClockSignal)):
+            self.comb += self.clkin.eq(clkin)
+        else:
+            raise ValueError
+        self.clkin_freq = freq
+        register_clkin_log(self.logger, clkin, freq)
+
+    def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True):
+        assert self.nclkouts < self.nclkouts_max
+        clkout = Signal()
+        self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
+        if with_reset:
+            # FIXME: Should use PLL's lock but does not seem stable.
+            self.specials += AsyncResetSynchronizer(cd, self.reset)
+        self.comb += cd.clk.eq(clkout)
+        create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
+        self.nclkouts += 1
+
+    def compute_config(self):
+        config = {}
+        for idiv in range(1, 64):
+            config["idiv"] = idiv
+            pfd_freq = self.clkin_freq/idiv
+            pfd_freq_min, pfd_freq_max = self.pfd_freq_range
+            if (pfd_freq < pfd_freq_min) or (pfd_freq > pfd_freq_max):
+                continue
+            for fdiv in range(1, 64):
+                out_freq = self.clkin_freq*fdiv/idiv
+                for odiv in [2, 4, 8, 16, 32, 48, 64, 80, 96, 112, 128]:
+                    config["odiv"] = odiv
+                    vco_freq = out_freq*odiv
+                    (vco_freq_min, vco_freq_max) = self.vco_freq_range
+                    if (vco_freq >= vco_freq_min*(1 + self.vco_margin) and
+                        vco_freq <= vco_freq_max*(1 - self.vco_margin)):
+                            for _n, (clk, f, p, _m) in sorted(self.clkouts.items()):
+                                if abs(out_freq - f) <= f*_m:
+                                    config["clk{}_freq".format(_n)] = out_freq
+                                    config["vco"]  = vco_freq
+                                    config["fdiv"] = fdiv
+                                    compute_config_log(self.logger, config)
+                                    return config
+        raise ValueError("No PLL config found")
+
+    def do_finalize(self):
+        assert hasattr(self, "clkin")
+        assert len(self.clkouts) == 1
+        config = self.compute_config()
+        # Based on UG286-1.3E Note.
+        self.params.update(
+            # Parameters.
+            p_DEVICE           = self.device,              # FPGA Device.
+            p_FCLKIN           = str(self.clkin_freq/1e6), # Clk Input frequency (MHz).
+            p_DYN_IDIV_SEL     = "false",                  # Disable dynamic IDIV.
+            p_IDIV_SEL         = config["idiv"]-1,         # Static IDIV value (1-64).
+            p_DYN_FBDIV_SEL    = "false",                  # Disable dynamic FBDIV.
+            p_FBDIV_SEL        = config["fdiv"]-1,         # Static FBDIV value (1-64).
+            p_DYN_ODIV_SEL     = "false",                  # Disable dynamic ODIV.
+            p_ODIV_SEL         = config["odiv"],           # Static ODIV value.
+            p_PSDA_SEL         = "0000",                   # -
+            p_DYN_DA_EN        = "false",                  # -
+            p_DUTYDA_SEL       = "1000",                   # -
+            p_CLKOUT_FT_DIR    = 1,                        # -
+            p_CLKOUTP_FT_DIR   = 1,                        # -
+            p_CLKOUT_DLY_STEP  = 0,                        # -
+            p_CLKOUTP_DLY_STEP = 0,                        # -
+            p_CLKFB_SEL        = "internal",               # Clk Feedback type (internal, external).
+            p_CLKOUT_BYPASS    = "false",                  # Clk Input to CLKOUT bypass.
+            p_CLKOUTP_BYPASS   = "false",                  # Clk Input to CLKOUTP bypass.
+            p_CLKOUTD_BYPASS   = "false",                  # Clk Input to CLKOUTD bypass.
+            p_DYN_SDIV_SEL     = 2,                        # Disable dynamic SDIV.
+            p_CLKOUTD_SRC      = "CLKOUT",                 # Recopy CLKOUT to CLKOUTD.
+            p_CLKOUTD3_SRC     = "CLKOUT",                 # Recopy CLKOUT to CLKOUTD3.
+
+            # Inputs.
+            i_CLKIN   = self.clkin, # Clk Input.
+            i_CLKFB   = 0,          # Clk Feedback.
+            i_RESET   = self.reset, # PLL Reset.
+            i_RESET_P = 0,          # PLL Power Down.
+            i_ODSEL   = 0,          # Dynamic ODIV control.
+            i_FBDSEL  = 0,          # Dynamic IDIV control.
+            i_IDSEL   = 0,          # Dynamic FDIV control.
+            i_PSDA    = 0,          # Dynamic phase control.
+            i_DUTYDA  = 0,          # Dynamic duty cycle control.
+            i_FDLY    = 0,          # Dynamic CLKOUTP delay control.
+            i_VREN    = 1,
+        )
+        clk0, f0, p0, m0 = self.clkouts[0]
+        self.params.update(
+            # Outputs.
+            o_LOCK     = self.locked, # PLL lock status.
+            o_CLKOUT   = clk0,        # Clock output.
+            o_CLKOUTP  = Open(),      # Clock output (With phase and duty cycle adjustement).
+            o_CLKOUTD  = Open(),      # Clock divided from CLKOUT and CLKOUTP (controlled by SDIV).
+            o_CLKOUTD3 = Open(),      # Clock divided from CLKOUT and CLKOUTP (constant division of 3).
+        )
+        self.specials += Instance("PLLVR", **self.params)

litex/soc/cores/clock/lattice_ecp5.py

@@ -97,6 +97,9 @@ class ECP5PLL(Module):
                                     break
                             if not valid:
                                 all_valid = False
+                        if self.nclkouts == self.nclkouts_max and not config["clkfb"]:
+                            # If there is no output suitable for feedback and no spare, not valid
+                            all_valid = False
                     else:
                         all_valid = False
                     if all_valid:
@@ -159,4 +162,6 @@ class ECP5PLL(Module):
             self.params[f"p_CLKO{n_to_l[n]}_FPHASE"] = 0
             self.params[f"p_CLKO{n_to_l[n]}_CPHASE"] = cphase
             self.params[f"o_CLKO{n_to_l[n]}"]        = clk
+            if f > 0:  # i.e. not a feedback-only clock
+                self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))
         self.specials += Instance("EHXPLLL", **self.params)

litex/soc/cores/clock/xilinx_s6.py

@@ -37,7 +37,6 @@ class S6PLL(XilinxClocking):
             p_BANDWIDTH      = "OPTIMIZED",
             p_COMPENSATION   = "INTERNAL",
             i_RST            = self.reset,
-            i_PWRDWN         = self.power_down,
             o_LOCKED         = self.locked,
 
             # VCO.

litex/soc/cores/cpu/blackparrot/crt0.S

@@ -53,7 +53,7 @@ trap_entry:
 
 
 crt_init:
-  la sp, _fstack + 8
+  la sp, _fstack
   la a0, trap_entry
   csrw mtvec, a0
 

litex/soc/cores/cpu/cv32e40p/crt0.S

@@ -90,7 +90,7 @@ trap_entry:
 
 
 crt_init:
-  la sp, _fstack + 4
+  la sp, _fstack
   la a0, vector_table
   csrw mtvec, a0
 

litex/soc/cores/cpu/microwatt/core.py

@@ -30,7 +30,7 @@ class Microwatt(CPU):
     variants             = CPU_VARIANTS
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
+    gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu", "ppc64le-linux", "ppc64le-linux-musl")
     linker_output_format = "elf64-powerpcle"
     nop                  = "nop"
     io_regions           = {0xc0000000: 0x10000000} # Origin, Length.
@@ -58,7 +58,6 @@ class Microwatt(CPU):
         flags += "-mlittle-endian "
         flags += "-mstrict-align "
         flags += "-fno-stack-protector "
-        flags += "-mcmodel=small "
         flags += "-D__microwatt__ "
         return flags
 

litex/soc/cores/cpu/rocket/boot-helper.S

@@ -1,4 +1,18 @@
 .section    .text, "ax", @progbits
-.global     boot_helper
+.global boot_helper
+.global smp_ap_args
+.global smp_ap_target
+.global smp_ap_ready
+
 boot_helper:
-	jr x13
+  // boot core saves args and jump target for ap cores:
+  sd a0, smp_ap_args, t1
+  sd a1, smp_ap_args+8, t1
+  sd a2, smp_ap_args+16, t1
+  sd a3, smp_ap_target, t1
+  fence w, w
+  // notify application cores to proceed with boot:
+  li t0, 1
+  sd t0, smp_ap_ready, t1
+  // boot core now also ready to boot:
+  jr a3

litex/soc/cores/cpu/rocket/core.py

@@ -45,9 +45,12 @@ class Open(Signal): pass
 CPU_VARIANTS = {
     "standard": "freechips.rocketchip.system.LitexConfig",
     "linux":    "freechips.rocketchip.system.LitexLinuxConfig",
+    "linux4":   "freechips.rocketchip.system.LitexLinux4Config",
     "linuxd":   "freechips.rocketchip.system.LitexLinuxDConfig",
     "linuxq":   "freechips.rocketchip.system.LitexLinuxQConfig",
     "full":     "freechips.rocketchip.system.LitexFullConfig",
+    "full4d":   "freechips.rocketchip.system.LitexFull4DConfig",
+    "full4q":   "freechips.rocketchip.system.LitexFull4QConfig",
 }
 
 # GCC Flags-----------------------------------------------------------------------------------------
@@ -55,20 +58,26 @@ CPU_VARIANTS = {
 GCC_FLAGS = {
     "standard": "-march=rv64imac   -mabi=lp64 ",
     "linux":    "-march=rv64imac   -mabi=lp64 ",
+    "linux4":   "-march=rv64imac   -mabi=lp64 ",
     "linuxd":   "-march=rv64imac   -mabi=lp64 ",
     "linuxq":   "-march=rv64imac   -mabi=lp64 ",
     "full":     "-march=rv64imafdc -mabi=lp64 ",
+    "full4d":   "-march=rv64imafdc -mabi=lp64 ",
+    "full4q":   "-march=rv64imafdc -mabi=lp64 ",
 }
 
-# AXI Data-Widths ----------------------------------------------------------------------------------
+# CPU Size Params ----------------------------------------------------------------------------------
 
-AXI_DATA_WIDTHS = {
-    # Variant : (mem, mmio)
-    "standard": ( 64,  64),
-    "linux":    ( 64,  64),
-    "linuxd":   (128,  64),
-    "linuxq":   (256,  64),
-    "full":     ( 64,  64),
+CPU_SIZE_PARAMS = {
+    # Variant : (mem_dw, mmio_dw, num_cores)
+    "standard": (    64,      64,         1),
+    "linux":    (    64,      64,         1),
+    "linux4":   (    64,      64,         4),
+    "linuxd":   (   128,      64,         1),
+    "linuxq":   (   256,      64,         1),
+    "full":     (    64,      64,         1),
+    "full4d":   (   128,      64,         4),
+    "full4q":   (   256,      64,         4),
 }
 
 # Rocket RV64 --------------------------------------------------------------------------------------
@@ -111,7 +120,7 @@ class RocketRV64(CPU):
         self.reset     = Signal()
         self.interrupt = Signal(4)
 
-        mem_dw, mmio_dw = AXI_DATA_WIDTHS[self.variant]
+        mem_dw, mmio_dw, num_cores = CPU_SIZE_PARAMS[self.variant]
 
         self.mem_axi   =  mem_axi = axi.AXIInterface(data_width=mem_dw,  address_width=32, id_width=4)
         self.mmio_axi  = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4)
@@ -132,7 +141,6 @@ class RocketRV64(CPU):
             i_reset = ResetSignal("sys") | self.reset,
 
             # Debug (ignored).
-            i_resetctrl_hartIsInReset_0           = Open(),
             i_debug_clock                         = 0,
             i_debug_reset                         = ResetSignal() | self.reset,
             o_debug_clockeddmi_dmi_req_ready      = Open(),
@@ -282,14 +290,14 @@ class RocketRV64(CPU):
             o_l2_frontend_bus_axi4_0_r_bits_resp   = l2fb_axi.r.resp,
             o_l2_frontend_bus_axi4_0_r_bits_last   = l2fb_axi.r.last,
         )
+        # additional per-core debug signals:
+        self.cpu_params.update({'i_resetctrl_hartIsInReset_%s'%i : Open() for i in range(num_cores)})
 
         # Adapt AXI interfaces to Wishbone.
-        mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
-        self.comb += mmio_a2w.reset.eq(ResetSignal() | self.reset) # Note: Must be reset with the CPU.
+        mmio_a2w = axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0)
         self.submodules += mmio_a2w
 
-        l2fb_a2w = ResetInserter()(axi.Wishbone2AXI(l2fb_wb, l2fb_axi, base_address=0))
-        self.comb += l2fb_a2w.reset.eq(ResetSignal() | self.reset) # Note: Must be reset with the CPU.
+        l2fb_a2w = axi.Wishbone2AXI(l2fb_wb, l2fb_axi, base_address=0)
         self.submodules += l2fb_a2w
 
         # Add Verilog sources.

litex/soc/cores/cpu/rocket/crt0.S

@@ -2,6 +2,10 @@
 .global isr
 .global _start
 
+.global smp_ap_args
+.global smp_ap_target
+.global smp_ap_ready
+
 _start:
   j crt_init
   nop
@@ -53,38 +57,66 @@ trap_entry:
 
 
 crt_init:
-  la sp, _fstack + 8
-  la a0, trap_entry
-  csrw mtvec, a0
+  la sp, _fstack
+  sd zero, smp_ap_ready, t0
+  la t0, trap_entry
+  csrw mtvec, t0
+
+smp_select_bp:
+  csrr a0, mhartid
+  beqz a0, data_init  // hart 0 is bp, everyone else is ap
+
+smp_ap_loop:
+  ld t0, smp_ap_ready
+  beqz t0, smp_ap_loop
+smp_ap_boot:
+  fence r, r
+  fence.i  // i$ flush
+  ld a0, smp_ap_args     // hart ID (but next-stage loads its own)
+  ld a1, smp_ap_args+8   // DTB pointer (if provded by litex bios)
+  ld a2, smp_ap_args+16
+  ld a3, smp_ap_target
+  jr a3
+smp_ap_done:
 
 data_init:
-  la a0, _fdata
-  la a1, _edata
-  la a2, _fdata_rom
+  la t0, _fdata
+  la t1, _edata
+  la t2, _fdata_rom
 data_loop:
-  beq a0,a1,data_done
-  ld a3,0(a2)
-  sd a3,0(a0)
-  add a0,a0,8
-  add a2,a2,8
+  beq t0,t1,data_done
+  ld t3,0(t2)
+  sd t3,0(t0)
+  add t0,t0,8
+  add t2,t2,8
   j data_loop
 data_done:
 
 bss_init:
-  la a0, _fbss
-  la a1, _ebss
+  la t0, _fbss
+  la t1, _ebss
 bss_loop:
-  beq a0,a1,bss_done
-  sd zero,0(a0)
-  add a0,a0,8
+  beq t0,t1,bss_done
+  sd zero,0(t0)
+  add t0,t0,8
   j bss_loop
 bss_done:
 
   call plic_init // initialize external interrupt controller
-  li a0, 0x800   // external interrupt sources only (using LiteX timer);
+  li t0, 0x800   // external interrupt sources only (using LiteX timer);
                  // NOTE: must still enable mstatus.MIE!
-  csrw mie,a0
+  csrw mie,t0
 
   call main
 inf_loop:
   j inf_loop
+
+.bss
+smp_ap_args:
+  .dword 0
+  .dword 0
+  .dword 0
+smp_ap_target:
+  .dword 0
+smp_ap_ready:
+  .dword 0

litex/soc/cores/cpu/vexriscv/core.py

@@ -135,6 +135,7 @@ class VexRiscv(CPU, AutoCSR):
 
         # # #
 
+        # CPU Instance.
         self.cpu_params = dict(
             i_clk                    = ClockSignal("sys"),
             i_reset                  = ResetSignal("sys") | self.reset,
@@ -168,9 +169,11 @@ class VexRiscv(CPU, AutoCSR):
             i_dBusWishbone_ERR      = dbus.err
         )
 
+        # Add Timer (Optional).
         if with_timer:
             self.add_timer()
 
+        # Add Debug (Optional).
         if "debug" in variant:
             self.add_debug()
 
@@ -287,7 +290,6 @@ class VexRiscv(CPU, AutoCSR):
                 ("valid", 1),
                 ("ready", 1),
                 ("payload", [
-                    ("response_ok", 1),
                     ("outputs_0", 32),
                 ]),
             ]),
@@ -305,7 +307,6 @@ class VexRiscv(CPU, AutoCSR):
             i_cmd_payload_inputs_1     = cfu_bus.cmd.payload.inputs_1,
             o_rsp_valid                = cfu_bus.rsp.valid,
             i_rsp_ready                = cfu_bus.rsp.ready,
-            o_rsp_payload_response_ok  = cfu_bus.rsp.payload.response_ok,
             o_rsp_payload_outputs_0    = cfu_bus.rsp.payload.outputs_0,
             i_clk                      = ClockSignal("sys"),
             i_reset                    = ResetSignal("sys"),
@@ -321,7 +322,6 @@ class VexRiscv(CPU, AutoCSR):
             o_CfuPlugin_bus_cmd_payload_inputs_1     = cfu_bus.cmd.payload.inputs_1,
             i_CfuPlugin_bus_rsp_valid                = cfu_bus.rsp.valid,
             o_CfuPlugin_bus_rsp_ready                = cfu_bus.rsp.ready,
-            i_CfuPlugin_bus_rsp_payload_response_ok  = cfu_bus.rsp.payload.response_ok,
             i_CfuPlugin_bus_rsp_payload_outputs_0    = cfu_bus.rsp.payload.outputs_0,
         )
 
@@ -332,9 +332,24 @@ class VexRiscv(CPU, AutoCSR):
         platform.add_source(os.path.join(vdir, cpu_filename))
 
     def add_soc_components(self, soc, soc_region_cls):
+        # Connect Debug interface to SoC.
         if "debug" in self.variant:
-            soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(
-                origin=soc.mem_map.get("vexriscv_debug"), size=0x100, cached=False))
+            soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=
+                soc_region_cls(
+                    origin = soc.mem_map.get("vexriscv_debug"),
+                    size   = 0x100,
+                    cached = False
+                )
+            )
+
+        # Pass I/D Caches info to software.
+        base_variant = str(self.variant.split('+')[0])
+        # DCACHE is present on all variants except minimal and lite.
+        if not base_variant in ["minimal", "lite"]:
+            soc.add_config("CPU_HAS_DCACHE")
+        # ICACHE is present on all variants except minimal.
+        if not base_variant in ["minimal"]:
+            soc.add_config("CPU_HAS_ICACHE")
 
     def use_external_variant(self, variant_filename):
         self.external_variant = True

litex/soc/cores/cpu/vexriscv/crt0.S

@@ -54,7 +54,7 @@ trap_entry:
 
 
 crt_init:
-  la sp, _fstack + 4
+  la sp, _fstack
   la a0, trap_entry
   csrw mtvec, a0
 

litex/soc/cores/cpu/vexriscv/system.h

@@ -11,9 +11,7 @@ extern "C" {
 
 __attribute__((unused)) static void flush_cpu_icache(void)
 {
-#if defined(CONFIG_CPU_VARIANT_MINIMAL)
-  /* No instruction cache */
-#else
+#if defined(CONFIG_CPU_HAS_ICACHE)
   asm volatile(
     ".word(0x100F)\n"
     "nop\n"
@@ -27,9 +25,7 @@ __attribute__((unused)) static void flush_cpu_icache(void)
 
 __attribute__((unused)) static void flush_cpu_dcache(void)
 {
-#if defined(CONFIG_CPU_VARIANT_MINIMAL) || defined(CONFIG_CPU_VARIANT_LITE)
-  /* No data cache */
-#else
+#if defined(CONFIG_CPU_HAS_DCACHE)
   asm volatile(".word(0x500F)\n");
 #endif
 }

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -419,8 +419,6 @@ class VexRiscvSMP(CPU):
     def add_memory_buses(self, address_width, data_width):
         VexRiscvSMP.litedram_width = data_width
 
-        VexRiscvSMP.generate_cluster_name()
-
         from litedram.common import LiteDRAMNativePort
         if(not VexRiscvSMP.wishbone_memory):
             ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width)
@@ -457,6 +455,7 @@ class VexRiscvSMP(CPU):
 
     def do_finalize(self):
         assert hasattr(self, "reset_address")
+        VexRiscvSMP.generate_cluster_name()
         self.specials += Instance(self.cluster_name, **self.cpu_params)
 
         # Add Verilog sources

litex/soc/cores/cpu/vexriscv_smp/crt0.S

@@ -58,11 +58,27 @@ trap_entry:
   .text
 
 crt_init:
-  la sp, _fstack + 4
+  la sp, _fstack
   la a0, trap_entry
   csrw mtvec, a0
   sw x0, smp_lottery_lock, a1
 
+smp_tyranny:
+  csrr a0, mhartid
+  beqz a0, data_init
+
+smp_slave:
+  lw a0, smp_lottery_lock
+  beqz a0, smp_slave
+  fence r, r
+
+  .word(0x100F) //i$ flush
+  lw x10, smp_lottery_args
+  lw x11, smp_lottery_args+4
+  lw x12, smp_lottery_args+8
+  lw x13, smp_lottery_target
+  jr x13
+
 data_init:
   la a0, _fdata
   la a1, _edata
@@ -76,23 +92,6 @@ data_loop:
   j data_loop
 data_done:
 
-smp_tyranny:
-  csrr a0, mhartid
-  beqz a0, bss_init
-  call smp_slave
-
-smp_slave:
-  lw a0, smp_lottery_lock
-  beqz a0, smp_slave
-  fence r, r
-
-  .word(0x100F) //i$ flush
-  lw x10, smp_lottery_args
-  lw x11, smp_lottery_args+4
-  lw x12, smp_lottery_args+8
-  lw x13, smp_lottery_target
-  jr x13
-
 bss_init:
   la a0, _fbss
   la a1, _ebss

litex/soc/cores/gpio.py

@@ -73,20 +73,29 @@ class GPIOInOut(Module):
 
 class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
     def __init__(self, pads, with_irq=False):
-        assert isinstance(pads, Signal)
-        nbits     = len(pads)
+        assert isinstance(pads, Signal) or isinstance(pads, Record)
+        nbits = len(pads) if isinstance(pads, Signal) else len(pads.o)
+
         self._oe  = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
         self._in  = CSRStatus(nbits,  description="GPIO Input(s) Status.")
         self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
 
         # # #
 
-        for i in range(nbits):
-            t = TSTriple()
-            self.specials += t.get_tristate(pads[i])
-            self.comb += t.oe.eq(self._oe.storage[i])
-            self.comb += t.o.eq(self._out.storage[i])
-            self.specials += MultiReg(t.i, self._in.status[i])
+        if isinstance(pads, Signal):
+            # Proper inout IOs.
+            for i in range(nbits):
+                t = TSTriple()
+                self.specials += t.get_tristate(pads[i])
+                self.comb += t.oe.eq(self._oe.storage[i])
+                self.comb += t.o.eq(self._out.storage[i])
+                self.specials += MultiReg(t.i, self._in.status[i])
+        else:
+            # Tristate inout IOs (For external tristate IO chips or simulation).
+            for i in range(nbits):
+                self.comb += pads.oe[i].eq(self._oe.storage[i])
+                self.comb += pads.o[i].eq(self._out.storage[i])
+                self.specials += MultiReg(pads.i[i], self._in.status[i])
 
         if with_irq:
             self.add_irq(self._in.status)

litex/soc/cores/uart.py

@@ -57,6 +57,8 @@ class RS232PHYTX(Module):
 
         # # #
 
+        pads.tx.reset = 1
+
         data  = Signal(8, reset_less=True)
         count = Signal(4, reset_less=True)
 

litex/soc/cores/video.py

@@ -733,6 +733,38 @@ class VideoHDMI10to1Serializer(Module):
             o   = data_o,
         )
 
+class VideoHDMIPHY(Module):
+    def __init__(self, pads, clock_domain="sys", pn_swap=[]):
+        self.sink = sink = stream.Endpoint(video_data_layout)
+
+        # # #
+
+        # Always ack Sink, no backpressure.
+        self.comb += sink.ready.eq(1)
+
+        # Clocking + Pseudo Differential Signaling.
+        self.specials += DDROutput(i1=1, i2=0, o=pads.clk_p, clk=ClockSignal(clock_domain))
+
+        # Encode/Serialize Datas.
+        for color in ["r", "g", "b"]:
+
+            # TMDS Encoding.
+            encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder())
+            setattr(self.submodules, f"{color}_encoder", encoder)
+            self.comb += encoder.d.eq(getattr(sink, color))
+            self.comb += encoder.c.eq(Cat(sink.hsync, sink.vsync) if color == "r" else 0)
+            self.comb += encoder.de.eq(sink.de)
+
+            # 10:1 Serialization + Pseudo Differential Signaling.
+            c2d  = {"r": 0, "g": 1, "b": 2}
+            data = encoder.out if color not in pn_swap else ~encoder.out
+            serializer = VideoHDMI10to1Serializer(
+                data_i       = data,
+                data_o       = getattr(pads, f"data{c2d[color]}_p"),
+                clock_domain = clock_domain,
+            )
+            setattr(self.submodules, f"{color}_serializer", serializer)
+
 # HDMI (Xilinx Spartan6).
 
 class VideoS6HDMIPHY(Module):
@@ -926,36 +958,3 @@ class VideoS7GTPHDMIPHY(Module):
             setattr(self.submodules, f"gtp{color}", gtp)
             self.comb += gtp.tx_produce_pattern.eq(1)
             self.comb += gtp.tx_pattern.eq(cdc.source.data)
-
-# HDMI (Lattice ECP5).
-
-class VideoECP5HDMIPHY(Module):
-    def __init__(self, pads, clock_domain="sys"):
-        self.sink = sink = stream.Endpoint(video_data_layout)
-
-        # # #
-
-        # Always ack Sink, no backpressure.
-        self.comb += sink.ready.eq(1)
-
-        # Clocking + Pseudo Differential Signaling.
-        self.specials += DDROutput(i1=1, i2=0, o=pads.clk_p, clk=ClockSignal(clock_domain))
-
-        # Encode/Serialize Datas.
-        for color in ["r", "g", "b"]:
-
-            # TMDS Encoding.
-            encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder())
-            setattr(self.submodules, f"{color}_encoder", encoder)
-            self.comb += encoder.d.eq(getattr(sink, color))
-            self.comb += encoder.c.eq(Cat(sink.hsync, sink.vsync) if color == "r" else 0)
-            self.comb += encoder.de.eq(sink.de)
-
-            # 10:1 Serialization + Pseudo Differential Signaling.
-            c2d   = {"r": 0, "g": 1, "b": 2}
-            serializer = VideoHDMI10to1Serializer(
-                data_i       = encoder.out,
-                data_o       = getattr(pads, f"data{c2d[color]}_p"),
-                clock_domain = clock_domain,
-            )
-            setattr(self.submodules, f"{color}_serializer", serializer)

litex/soc/integration/builder.py

@@ -2,7 +2,7 @@
 # This file is part of LiteX.
 #
 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
-# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2015-2021 Florent Kermarrec <florent@enjoy-digital.fr>
 # This file is Copyright (c) 2018-2019 Antmicro <www.antmicro.com>
 # This file is Copyright (c) 2018 Sergiusz Bazanski <q3k@q3k.org>
 # This file is Copyright (c) 2016-2017 Tim 'mithro' Ansell <mithro@mithis.com>
@@ -27,12 +27,18 @@ from litex.soc.cores import cpu
 def _makefile_escape(s):
     return s.replace("\\", "\\\\")
 
-def _create_dir(d):
-    os.makedirs(os.path.realpath(d), exist_ok=True)
+def _create_dir(d, remove_if_exists=False):
+    dir_path = os.path.realpath(d)
+    if remove_if_exists and os.path.exists(dir_path):
+        shutil.rmtree(dir_path)
+    os.makedirs(dir_path, exist_ok=True)
 
 # Software Packages --------------------------------------------------------------------------------
 
 soc_software_packages = [
+    # picolibc
+    "libc",
+
     # Compiler-RT.
     "libcompiler_rt",
 
@@ -50,7 +56,7 @@ soc_software_packages = [
 
 # Builder ------------------------------------------------------------------------------------------
 
-soc_directory         = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
+soc_directory = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
 
 class Builder:
     def __init__(self, soc,
@@ -103,14 +109,11 @@ class Builder:
         self.generate_doc = generate_doc
 
         # List software packages and libraries.
-        self.software_packages = []
+        self.software_packages  = []
         self.software_libraries = []
 
         for name in soc_software_packages:
             self.add_software_package(name)
-
-            if name == "libbase":
-                name += "-nofloat"
             self.add_software_library(name)
 
     def add_software_package(self, name, src_dir=None):
@@ -121,46 +124,48 @@ class Builder:
     def add_software_library(self, name):
         self.software_libraries.append(name)
 
-    def _generate_includes(self):
+    def _get_variables_contents(self):
+        variables_contents = []
+        def define(k, v):
+            variables_contents.append("{}={}".format(k, _makefile_escape(v)))
+
+        # Define packages and libraries.
+        define("PACKAGES", " ".join(name for name, src_dir in self.software_packages))
+        define("PACKAGE_DIRS", " ".join(src_dir for name, src_dir in self.software_packages))
+        define("LIBS", " ".join(self.software_libraries))
+
+        # Define the CPU variables.
+        for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software):
+            define(k, v)
+
+        # Define the SoC/Picolibc/Compiler-RT/Software/Include directories.
+        define("SOC_DIRECTORY", soc_directory)
+        picolibc_directory = get_data_mod("software", "picolibc").data_location
+        define("PICOLIBC_DIRECTORY", picolibc_directory)
+        compiler_rt_directory = get_data_mod("software", "compiler_rt").data_location
+        define("COMPILER_RT_DIRECTORY", compiler_rt_directory)
+        variables_contents.append("export BUILDINC_DIRECTORY")
+        define("BUILDINC_DIRECTORY", self.include_dir)
+        for name, src_dir in self.software_packages:
+            define(name.upper() + "_DIRECTORY", src_dir)
+
+        # Define the BIOS Options.
+        for bios_option in self.bios_options:
+            assert bios_option in ["TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"]
+            define(bios_option, "1")
+
+        return "\n".join(variables_contents)
+
+    def _generate_includes(self, with_bios=True):
         # Generate Include/Generated directories.
         _create_dir(self.include_dir)
         _create_dir(self.generated_dir)
 
         # Generate BIOS files when the SoC uses it.
-        with_bios = self.soc.cpu_type not in [None, "zynq7000"]
         if with_bios:
-            self.add_software_package("bios")
-
             # Generate Variables to variables.mak.
-            variables_contents = []
-            def define(k, v):
-                variables_contents.append("{}={}".format(k, _makefile_escape(v)))
-
-            # Define packages and libraries.
-            define("PACKAGES", " ".join(name for name, src_dir in self.software_packages))
-            define("PACKAGE_DIRS", " ".join(src_dir for name, src_dir in self.software_packages))
-            define("LIBS", " ".join(self.software_libraries))
-
-            # Define the CPU variables.
-            for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software):
-                define(k, v)
-
-            # Define the SoC/Compiler-RT/Software/Include directories.
-            define("SOC_DIRECTORY",         soc_directory)
-            compiler_rt_directory = get_data_mod("software", "compiler_rt").data_location
-            define("COMPILER_RT_DIRECTORY", compiler_rt_directory)
-            variables_contents.append("export BUILDINC_DIRECTORY")
-            define("BUILDINC_DIRECTORY", self.include_dir)
-            for name, src_dir in self.software_packages:
-                define(name.upper() + "_DIRECTORY", src_dir)
-
-            # Define the BIOS Options.
-            for bios_option in self.bios_options:
-                assert bios_option in ["TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"]
-                define(bios_option, "1")
-
-            # Write to variables.mak.
-            write_to_file(os.path.join(self.generated_dir, "variables.mak"), "\n".join(variables_contents))
+            variables_contents = self._get_variables_contents()
+            write_to_file(os.path.join(self.generated_dir, "variables.mak"), variables_contents)
 
             # Generate Output Format to output_format.ld.
             output_format_contents = export.get_linker_output_format(self.soc.cpu)
@@ -194,7 +199,7 @@ class Builder:
         git_contents = export.get_git_header()
         write_to_file(os.path.join(self.generated_dir, "git.h"), git_contents)
 
-        # Generate LiteDRAM C header to sdram_phy.h when the SoC use it.
+        # Generate LiteDRAM C header to sdram_phy.h when the SoC use it
         if hasattr(self.soc, "sdram"):
             from litedram.init import get_sdram_phy_c_header
             sdram_contents = get_sdram_phy_c_header(
@@ -253,15 +258,30 @@ class Builder:
         # Pass Output Directory to Platform.
         self.soc.platform.output_dir = self.output_dir
 
-        # Create Gateware/Software directories.
+        # Check if BIOS is used and add software package if so.
+        with_bios = self.soc.cpu_type not in [None, "zynq7000"]
+        if with_bios:
+            self.add_software_package("bios")
+
+        # Create Gateware directory.
         _create_dir(self.gateware_dir)
-        _create_dir(self.software_dir)
+
+        # Create Software directory.
+        # First check if software needs a full re-build and remove software dir if so.
+        if self.soc.cpu_type is not None:
+            software_full_rebuild  = False
+            software_variables_mak = os.path.join(self.generated_dir, "variables.mak")
+            if os.path.exists(software_variables_mak):
+                old_variables_contents = open(software_variables_mak).read()
+                new_variables_contents = self._get_variables_contents()
+                software_full_rebuild  = (old_variables_contents != new_variables_contents)
+            _create_dir(self.software_dir, remove_if_exists=software_full_rebuild)
 
         # Finalize the SoC.
         self.soc.finalize()
 
         # Generate Software Includes/Files.
-        self._generate_includes()
+        self._generate_includes(with_bios=with_bios)
 
         # Export SoC Mapping.
         self._generate_csr_map()

litex/soc/integration/export.py

@@ -18,6 +18,8 @@
 
 import os
 import json
+import time
+import datetime
 import inspect
 from shutil import which
 from sysconfig import get_platform
@@ -33,26 +35,22 @@ from litex.soc.doc.module import gather_submodules, ModuleNotDocumented, Documen
 from litex.soc.doc.csr import DocumentedCSRRegion
 from litex.soc.interconnect.csr import _CompoundCSR
 
-# for generating a timestamp in the description field, if none is otherwise given
-import datetime
-import time
-
 # CPU files ----------------------------------------------------------------------------------------
 
 def get_cpu_mak(cpu, compile_software):
-    # select between clang and gcc
+    # Select between CLANG and GCC.
     clang = os.getenv("CLANG", "")
     if clang != "":
         clang = bool(int(clang))
     else:
         clang = None
-    if not hasattr(cpu, "clang_triple"):
+    if cpu.clang_triple is None:
         if clang:
-            raise ValueError(cpu.name + "not supported with clang.")
+            raise ValueError(cpu.name + " is not supported with CLANG.")
         else:
             clang = False
     else:
-        # Default to gcc unless told otherwise
+        # Default to gcc unless told otherwise.
         if clang is None:
             clang = False
     assert isinstance(clang, bool)
@@ -63,7 +61,7 @@ def get_cpu_mak(cpu, compile_software):
         triple = cpu.gcc_triple
         flags = cpu.gcc_flags
 
-    # select triple when more than one
+    # Select triple when more than one.
     def select_triple(triple):
         r = None
         if not isinstance(triple, tuple):
@@ -74,7 +72,7 @@ def get_cpu_mak(cpu, compile_software):
         p = get_platform()
         for i in range(len(triple)):
             t = triple[i]
-            # use native toolchain if host and target platforms are the same
+            # Use native toolchain if host and target platforms are the same.
             if t == 'riscv64-unknown-elf' and p == 'linux-riscv64':
                 r = '--native--'
                 break
@@ -90,25 +88,25 @@ def get_cpu_mak(cpu, compile_software):
             raise OSError(msg)
         return r
 
-    # return informations
+    # Return informations.
     return [
-        ("TRIPLE", select_triple(triple)),
-        ("CPU", cpu.name),
-        ("CPUFLAGS", flags),
+        ("TRIPLE",        select_triple(triple)),
+        ("CPU",           cpu.name),
+        ("CPUFLAGS",      flags),
         ("CPUENDIANNESS", cpu.endianness),
-        ("CLANG", str(int(clang))),
+        ("CLANG",         str(int(clang))),
         ("CPU_DIRECTORY", os.path.dirname(inspect.getfile(cpu.__class__))),
     ]
 
 
 def get_linker_output_format(cpu):
-    return "OUTPUT_FORMAT(\"" + cpu.linker_output_format + "\")\n"
+    return f"OUTPUT_FORMAT(\"{cpu.linker_output_format}\")\n"
 
 
 def get_linker_regions(regions):
     r = "MEMORY {\n"
     for name, region in regions.items():
-        r += "\t{} : ORIGIN = 0x{:08x}, LENGTH = 0x{:08x}\n".format(name, region.origin, region.length)
+        r += f"\t{name} : ORIGIN = 0x{region.origin:08x}, LENGTH = 0x{region.length:08x}\n"
     r += "}\n"
     return r
 
@@ -119,8 +117,8 @@ def get_git_header():
     from litex.build.tools import get_migen_git_revision, get_litex_git_revision
     r = generated_banner("//")
     r += "#ifndef __GENERATED_GIT_H\n#define __GENERATED_GIT_H\n\n"
-    r += "#define MIGEN_GIT_SHA1 \"{}\"\n".format(get_migen_git_revision())
-    r += "#define LITEX_GIT_SHA1 \"{}\"\n".format(get_litex_git_revision())
+    r += f"#define MIGEN_GIT_SHA1 \"{get_migen_git_revision()}\"\n"
+    r += f"#define LITEX_GIT_SHA1 \"{get_litex_git_revision()}\"\n"
     r += "#endif\n"
     return r
 
@@ -128,9 +126,9 @@ def get_mem_header(regions):
     r = generated_banner("//")
     r += "#ifndef __GENERATED_MEM_H\n#define __GENERATED_MEM_H\n\n"
     for name, region in regions.items():
-        r += "#ifndef {name}_BASE\n".format(name=name.upper())
-        r += "#define {name}_BASE 0x{base:08x}L\n#define {name}_SIZE 0x{size:08x}\n".format(
-            name=name.upper(), base=region.origin, size=region.length)
+        r += f"#ifndef {name.upper()}_BASE\n"
+        r += f"#define {name.upper()}_BASE 0x{region.origin:08x}L\n"
+        r += f"#define {name.upper()}_SIZE 0x{region.length:08x}\n"
         r += "#endif\n\n"
 
     r += "#ifndef MEM_REGIONS\n"
@@ -175,14 +173,14 @@ def get_soc_header(constants, with_access_functions=True):
 def _get_rw_functions_c(reg_name, reg_base, nwords, busword, alignment, read_only, with_access_functions):
     r = ""
 
-    addr_str = "CSR_{}_ADDR".format(reg_name.upper())
-    size_str = "CSR_{}_SIZE".format(reg_name.upper())
-    r += "#define {} (CSR_BASE + {}L)\n".format(addr_str, hex(reg_base))
-    r += "#define {} {}\n".format(size_str, nwords)
+    addr_str = f"CSR_{reg_name.upper()}_ADDR"
+    size_str = f"CSR_{reg_name.upper()}_SIZE"
+    r += f"#define {addr_str} (CSR_BASE + {hex(reg_base)}L)\n"
+    r += f"#define {size_str} {nwords}\n"
 
     size = nwords*busword//8
     if size > 8:
-        # downstream should select appropriate `csr_[rd|wr]_buf_uintX()` pair!
+        # Downstream should select appropriate `csr_[rd|wr]_buf_uintX()` pair!
         return r
     elif size > 4:
         ctype = "uint64_t"
@@ -195,25 +193,25 @@ def _get_rw_functions_c(reg_name, reg_base, nwords, busword, alignment, read_onl
 
     stride = alignment//8;
     if with_access_functions:
-        r += "static inline {} {}_read(void) {{\n".format(ctype, reg_name)
+        r += f"static inline {ctype} {reg_name}_read(void) {{\n"
         if nwords > 1:
-            r += "\t{} r = csr_read_simple(CSR_BASE + {}L);\n".format(ctype, hex(reg_base))
+            r += f"\t{ctype} r = csr_read_simple(CSR_BASE + {reg_base}L);\n"
             for sub in range(1, nwords):
-                r += "\tr <<= {};\n".format(busword)
-                r += "\tr |= csr_read_simple(CSR_BASE + {}L);\n".format(hex(reg_base+sub*stride))
+                r += f"\tr <<= {busword};\n"
+                r += f"\tr |= csr_read_simple(CSR_BASE + {hex(reg_base+sub*stride)}L);\n"
             r += "\treturn r;\n}\n"
         else:
-            r += "\treturn csr_read_simple(CSR_BASE + {}L);\n}}\n".format(hex(reg_base))
+            r += f"\treturn csr_read_simple(CSR_BASE + {hex(reg_base)}L);\n}}\n"
 
         if not read_only:
-            r += "static inline void {}_write({} v) {{\n".format(reg_name, ctype)
+            r += f"static inline void {reg_name}_write({ctype} v) {{\n"
             for sub in range(nwords):
                 shift = (nwords-sub-1)*busword
                 if shift:
                     v_shift = "v >> {}".format(shift)
                 else:
                     v_shift = "v"
-                r += "\tcsr_write_simple({}, CSR_BASE + {}L);\n".format(v_shift, hex(reg_base+sub*stride))
+                r += f"\tcsr_write_simple({v_shift}, CSR_BASE + {hex(reg_base+sub*stride)}L);\n"
             r += "}\n"
     return r
 
@@ -232,12 +230,12 @@ def get_csr_header(regions, constants, csr_base=None, with_access_functions=True
         r += "#endif /* ! CSR_ACCESSORS_DEFINED */\n"
     csr_base = csr_base if csr_base is not None else regions[next(iter(regions))].origin
     r += "#ifndef CSR_BASE\n"
-    r += "#define CSR_BASE {}L\n".format(hex(csr_base))
+    r += f"#define CSR_BASE {hex(csr_base)}L\n"
     r += "#endif\n"
     for name, region in regions.items():
         origin = region.origin - csr_base
         r += "\n/* "+name+" */\n"
-        r += "#define CSR_"+name.upper()+"_BASE (CSR_BASE + "+hex(origin)+"L)\n"
+        r += f"#define CSR_{name.upper()}_BASE (CSR_BASE + {hex(origin)}L)\n"
         if not isinstance(region.obj, Memory):
             for csr in region.obj:
                 nr = (csr.size + region.busword - 1)//region.busword
@@ -248,10 +246,10 @@ def get_csr_header(regions, constants, csr_base=None, with_access_functions=True
                     for field in csr.fields.fields:
                         offset = str(field.offset)
                         size = str(field.size)
-                        r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_OFFSET "+offset+"\n"
-                        r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_SIZE "+size+"\n"
+                        r += f"#define CSR_{name.upper()}_{csr.name.upper()}_{field.name.upper()}_OFFSET {offset}\n"
+                        r += f"#define CSR_{name.upper()}_{csr.name.upper()}_{field.name.upper()}_SIZE {size}\n"
                         if with_access_functions and csr.size <= 32: # FIXME: Implement extract/read functions for csr.size > 32-bit.
-                            reg_name = name + "_" + csr.name.lower()
+                            reg_name   = name + "_" + csr.name.lower()
                             field_name = reg_name + "_" + field.name.lower()
                             r += "static inline uint32_t " + field_name + "_extract(uint32_t oldword) {\n"
                             r += "\tuint32_t mask = ((1 << " + size + ")-1);\n"
@@ -290,13 +288,16 @@ def get_csr_json(csr_regions={}, constants={}, mem_regions={}):
         region_origin = region.origin
         if not isinstance(region.obj, Memory):
             for csr in region.obj:
-                size = (csr.size + region.busword - 1)//region.busword
+                _size = (csr.size + region.busword - 1)//region.busword
+                _type = "rw"
+                if isinstance(csr, CSRStatus) and not hasattr(csr, "r"):
+                    _type = "ro"
                 d["csr_registers"][name + "_" + csr.name] = {
                     "addr": region_origin,
-                    "size": size,
-                    "type": "ro" if isinstance(csr, CSRStatus) else "rw"
+                    "size": _size,
+                    "type": _type
                 }
-                region_origin += alignment//8*size
+                region_origin += alignment//8*_size
 
     for name, value in constants.items():
         d["constants"][name.lower()] = value.lower() if isinstance(value, str) else value

litex/soc/integration/soc.py

@@ -233,13 +233,17 @@ class SoCBusHandler(Module):
         for _, search_region in search_regions.items():
             origin = search_region.origin
             while (origin + size) < (search_region.origin + search_region.size_pow2):
+                # Align Origin on Size.
+                if (origin%size):
+                    origin += (origin - origin%size)
+                    continue
                 # Create a Candidate.
                 candidate = SoCRegion(origin=origin, size=size, cached=cached)
                 overlap   = False
                 # Check Candidate does not overlap with allocated existing regions.
                 for _, allocated in self.regions.items():
                     if self.check_regions_overlap({"0": allocated, "1": candidate}) is not None:
-                        origin  = allocated.origin + allocated.size_pow2
+                        origin += size
                         overlap = True
                         break
                 if not overlap:
@@ -1329,12 +1333,10 @@ class LiteXSoC(SoC):
                         mem_wb  = wishbone.Interface(
                             data_width = self.cpu.mem_axi.data_width,
                             adr_width  = 32-log2_int(self.cpu.mem_axi.data_width//8))
-                        # FIXME: AXI2Wishbone FSMs must be reset with the CPU.
-                        mem_a2w = ResetInserter()(axi.AXI2Wishbone(
+                        mem_a2w = axi.AXI2Wishbone(
                             axi          = self.cpu.mem_axi,
                             wishbone     = mem_wb,
-                            base_address = 0))
-                        self.comb += mem_a2w.reset.eq(ResetSignal() | self.cpu.reset)
+                            base_address = 0)
                         self.submodules += mem_a2w
                         litedram_wb = wishbone.Interface(port.data_width)
                         self.submodules += LiteDRAMWishbone2Native(
@@ -1397,9 +1399,10 @@ class LiteXSoC(SoC):
 
     # Add Ethernet ---------------------------------------------------------------------------------
     def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False,
-        nrxslots       = 2,
-        ntxslots       = 2,
-        with_timestamp = False):
+        nrxslots                = 2,
+        ntxslots                = 2,
+        with_timestamp          = False,
+        with_timing_constraints = True):
         # Imports
         from liteeth.mac import LiteEthMAC
         from liteeth.phy.model import LiteEthPHYModel
@@ -1450,10 +1453,11 @@ class LiteXSoC(SoC):
 
     # Add Etherbone --------------------------------------------------------------------------------
     def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth",
-        mac_address  = 0x10e2d5000000,
-        ip_address   = "192.168.1.50",
-        udp_port     = 1234,
-        buffer_depth = 4):
+        mac_address             = 0x10e2d5000000,
+        ip_address              = "192.168.1.50",
+        udp_port                = 1234,
+        buffer_depth            = 4,
+        with_timing_constraints = True):
         # Imports
         from liteeth.core import LiteEthUDPIPCore
         from liteeth.frontend.etherbone import LiteEthEtherbone
@@ -1493,7 +1497,7 @@ class LiteXSoC(SoC):
                 self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
 
     # Add SPI Flash --------------------------------------------------------------------------------
-    def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, **kwargs):
+    def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, phy=None, rate="1:1", **kwargs):
         if module is None:
             # Use previous LiteX SPI Flash core with compat, will be deprecated at some point.
             from litex.compat.soc_add_spi_flash import add_spi_flash
@@ -1501,29 +1505,34 @@ class LiteXSoC(SoC):
         # LiteSPI.
         else:
             # Imports.
-            from litespi.phy.generic import LiteSPIPHY
             from litespi import LiteSPI
+            from litespi.phy.generic import LiteSPIPHY
             from litespi.opcodes import SpiNorFlashOpCodes
 
             # Checks/Parameters.
             assert mode in ["1x", "4x"]
             if clk_freq is None: clk_freq = self.sys_clk_freq
 
+            # PHY.
+            spiflash_phy = phy
+            if spiflash_phy is None:
+                self.check_if_exists(name + "_phy")
+                spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
+                spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq), rate=rate)
+                setattr(self.submodules, name + "_phy",  spiflash_phy)
+
             # Core.
-            self.check_if_exists(name + "_phy")
             self.check_if_exists(name + "_mmap")
-            spiflash_pads   = self.platform.request(name if mode == "1x" else name + mode)
-            spiflash_phy    = LiteSPIPHY(spiflash_pads, module, default_divisor=int(self.sys_clk_freq/clk_freq))
-            spiflash_core   = LiteSPI(spiflash_phy, clk_freq=clk_freq, mmap_endianness=self.cpu.endianness, **kwargs)
-            setattr(self.submodules, name + "_phy",  spiflash_phy)
+            spiflash_core = LiteSPI(spiflash_phy, mmap_endianness=self.cpu.endianness, **kwargs)
             setattr(self.submodules, name + "_core", spiflash_core)
             spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size)
             self.bus.add_slave(name=name, slave=spiflash_core.bus, region=spiflash_region)
 
             # Constants.
-            self.add_constant("SPIFLASH_MODULE_NAME",       module.name.upper())
+            self.add_constant("SPIFLASH_PHY_FREQUENCY", clk_freq)
+            self.add_constant("SPIFLASH_MODULE_NAME", module.name.upper())
             self.add_constant("SPIFLASH_MODULE_TOTAL_SIZE", module.total_size)
-            self.add_constant("SPIFLASH_MODULE_PAGE_SIZE",  module.page_size)
+            self.add_constant("SPIFLASH_MODULE_PAGE_SIZE", module.page_size)
             if SpiNorFlashOpCodes.READ_1_1_4 in module.supported_opcodes:
                 self.add_constant("SPIFLASH_MODULE_QUAD_CAPABLE")
             if SpiNorFlashOpCodes.READ_4_4_4 in module.supported_opcodes:

litex/soc/interconnect/axi.py

@@ -317,7 +317,7 @@ class AXIBurst2Beat(Module):
 
         beat_count  = Signal(8)
         beat_size   = Signal(8 + 4)
-        beat_offset = Signal(8 + 4)
+        beat_offset = Signal((8 + 4, True))
         beat_wrap   = Signal(8 + 4)
 
         # Compute parameters
@@ -352,8 +352,8 @@ class AXIBurst2Beat(Module):
                     )
                 ),
                 If((ax_burst.burst == BURST_WRAP) & (BURST_WRAP in capabilities),
-                    If(beat_offset == beat_wrap,
-                        beat_offset.eq(0)
+                    If((ax_beat.addr & beat_wrap) == beat_wrap,
+                        beat_offset.eq(beat_offset - beat_wrap)
                     )
                 )
             )

litex/soc/interconnect/packet.py

@@ -411,7 +411,7 @@ class PacketFIFO(Module):
 
         # Connect FIFOs to Source.
         self.comb += [
-            param_fifo.source.connect(source,   omit={"last",  "ready"}),
+            param_fifo.source.connect(source,   omit={"last",  "ready", "dummy"}),
             payload_fifo.source.connect(source, omit={"valid", "ready"}),
             param_fifo.source.ready.eq(  source.valid & source.last & source.ready),
             payload_fifo.source.ready.eq(source.valid &               source.ready),

litex/soc/interconnect/wishbone.py

@@ -6,6 +6,8 @@
 # Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
 # SPDX-License-Identifier: BSD-2-Clause
 
+"""Wishbone Classic support for LiteX (Standard HandShaking/Synchronous Feedback)"""
+
 from math import log2
 
 from functools import reduce

litex/soc/software/bios/Makefile

@@ -19,6 +19,7 @@ OBJECTS = isr.o			\
 	  cmd_liteeth.o		\
 	  cmd_litesdcard.o  \
 	  cmd_litesata.o    \
+	  sim_debug.o		\
 	  main.o
 
 ifneq "$(or $(TERM_NO_COMPLETE),$(TERM_MINI))" ""
@@ -56,9 +57,9 @@ bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS)
 
 vpath %.a $(PACKAGES:%=../%)
 
-%.elf: ../libbase/crt0.o $(LIBS:%=%.a)
+%.elf: crt0.o $(LIBS:%=%.a)
 	$(CC) $(LDFLAGS) -T $(BIOS_DIRECTORY)/linker.ld -N -o $@ \
-		../libbase/crt0.o \
+		crt0.o \
 		$(OBJECTS) \
 		$(PACKAGES:%=-L../%) \
 		-Wl,--whole-archive \
@@ -85,6 +86,9 @@ endif
 boot-helper.o: $(CPU_DIRECTORY)/boot-helper.S
 	$(assemble)
 
+crt0.o: $(CPU_DIRECTORY)/crt0.S
+	$(assemble)
+
 clean:
 	$(RM) $(OBJECTS) bios.elf bios.bin .*~ *~
 

litex/soc/software/bios/boot.c

@@ -10,10 +10,7 @@
 #include <stdio.h>
 #include <stdint.h>
 #include <stdlib.h>
-#include <console.h>
-#include <uart.h>
 #include <system.h>
-#include <crc.h>
 #include <string.h>
 #include <irq.h>
 
@@ -23,9 +20,13 @@
 
 #include "sfl.h"
 #include "boot.h"
-#include "jsmn.h"
 
-#include <progress.h>
+#include <libbase/uart.h>
+
+#include <libbase/console.h>
+#include <libbase/crc.h>
+#include <libbase/jsmn.h>
+#include <libbase/progress.h>
 
 #include <libliteeth/udp.h>
 #include <libliteeth/tftp.h>

litex/soc/software/bios/cmds/cmd_bios.c

@@ -2,15 +2,15 @@
 
 #include <stdio.h>
 #include <stdlib.h>
-#include <id.h>
-#include <crc.h>
 #include <system.h>
-#include <sim_debug.h>
+
+#include <libbase/crc.h>
 
 #include <generated/csr.h>
 
 #include "../command.h"
 #include "../helpers.h"
+#include "../sim_debug.h"
 
 /**
  * Command "help"
@@ -48,9 +48,17 @@ define_command(help, help_handler, "Print this help", SYSTEM_CMDS);
  */
 static void ident_handler(int nb_params, char **params)
 {
+	const int IDENT_SIZE = 256;
 	char buffer[IDENT_SIZE];
 
-	get_ident(buffer);
+#ifdef CSR_IDENTIFIER_MEM_BASE
+	int i;
+	for(i=0;i<IDENT_SIZE;i++)
+		buffer[i] = MMPTR(CSR_IDENTIFIER_MEM_BASE + CONFIG_CSR_ALIGNMENT/8*i);
+#else
+	buffer[0] = 0;
+#endif
+
 	printf("Ident: %s", *buffer ? buffer : "-");
 }
 

litex/soc/software/bios/cmds/cmd_i2c.c

@@ -5,7 +5,7 @@
 #include <stdbool.h>
 
 #include <generated/csr.h>
-#include <i2c.h>
+#include <libbase/i2c.h>
 
 #include "../command.h"
 #include "../helpers.h"

litex/soc/software/bios/cmds/cmd_litedram.c

@@ -4,11 +4,11 @@
 #include <stdlib.h>
 #include <stdbool.h>
 #include <string.h>
-#include <memtest.h>
+#include <libbase/memtest.h>
 
 #include <generated/csr.h>
 #include <generated/mem.h>
-#include <i2c.h>
+#include <libbase/i2c.h>
 
 #include <liblitedram/sdram.h>
 #include <liblitedram/bist.h>

litex/soc/software/bios/cmds/cmd_mem.c

@@ -2,7 +2,7 @@
 
 #include <stdio.h>
 #include <stdlib.h>
-#include <memtest.h>
+#include <libbase/memtest.h>
 
 #include <generated/csr.h>
 #include <generated/mem.h>
@@ -202,9 +202,10 @@ static void mem_speed_handler(int nb_params, char **params)
 	unsigned int *addr;
 	unsigned long size;
 	bool read_only = false;
+	bool random = false;
 
 	if (nb_params < 1) {
-		printf("mem_speed <addr> <size> [<readonly>]");
+		printf("mem_speed <addr> <size> [<readonly>] [<random>]");
 		return;
 	}
 
@@ -228,6 +229,14 @@ static void mem_speed_handler(int nb_params, char **params)
 		}
 	}
 
-	memspeed(addr, size, read_only);
+	if (nb_params >= 4) {
+		random = (bool) strtoul(params[3], &c, 0);
+		if (*c != 0) {
+			printf("Incorrect random value");
+			return;
+		}
+	}
+
+	memspeed(addr, size, read_only, random);
 }
 define_command(mem_speed, mem_speed_handler, "Test memory speed", MEM_CMDS);

litex/soc/software/bios/helpers.c

@@ -3,10 +3,11 @@
 // SPDX-License-Identifier: BSD-Source-Code
 
 #include <stdio.h>
-#include <console.h>
-#include <crc.h>
 #include <string.h>
 
+#include <libbase/console.h>
+#include <libbase/crc.h>
+
 #include "readline.h"
 #include "helpers.h"
 #include "command.h"
@@ -20,7 +21,7 @@ void dump_bytes(unsigned int *ptr, int count, unsigned long addr)
 	char *data = (char *)ptr;
 	int line_bytes = 0, i = 0;
 
-	putsnonl("Memory dump:");
+	fputs("Memory dump:", stdout);
 	while (count > 0) {
 		line_bytes =
 			(count > NUMBER_OF_BYTES_ON_A_LINE)?

litex/soc/software/bios/isr.c

@@ -7,7 +7,7 @@
 #include <generated/csr.h>
 #include <generated/soc.h>
 #include <irq.h>
-#include <uart.h>
+#include <libbase/uart.h>
 #include <stdio.h>
 
 #if defined(__microwatt__)

litex/soc/software/bios/linker.ld

@@ -85,7 +85,7 @@ SECTIONS
 	}
 }
 
-PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 8);
+PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram));
 
 PROVIDE(_fdata_rom = LOADADDR(.data));
 PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));

litex/soc/software/bios/main.c

@@ -17,13 +17,9 @@
 
 #include <stdio.h>
 #include <stdlib.h>
-#include <console.h>
 #include <string.h>
-#include <uart.h>
 #include <system.h>
-#include <id.h>
 #include <irq.h>
-#include <crc.h>
 
 #include "boot.h"
 #include "readline.h"
@@ -35,7 +31,11 @@
 #include <generated/mem.h>
 #include <generated/git.h>
 
-#include <spiflash.h>
+#include <libbase/console.h>
+#include <libbase/crc.h>
+
+#include <libbase/spiflash.h>
+#include <libbase/uart.h>
 
 #include <liblitedram/sdram.h>
 

litex/soc/software/bios/readline.c

@@ -13,9 +13,6 @@
 #include <string.h>
 #include <ctype.h>
 
-#include <console.h>
-#include <uart.h>
-
 #include "readline.h"
 #include "complete.h"
 
@@ -54,15 +51,15 @@ static int read_key(void)
 {
 	char c;
 	char esc[5];
-	c = readchar();
+	c = getchar();
 
 	if (c == 27) {
 		int i = 0;
-		esc[i++] = readchar();
-		esc[i++] = readchar();
+		esc[i++] = getchar();
+		esc[i++] = getchar();
 		if (isdigit(esc[1])) {
 			while(1) {
-				esc[i] = readchar();
+				esc[i] = getchar();
 				if (esc[i++] == '~')
 					break;
 				if (i == ARRAY_SIZE(esc))

litex/soc/software/bios/readline_simple.c

@@ -8,9 +8,6 @@
 #include <string.h>
 #include <ctype.h>
 
-#include <console.h>
-#include <uart.h>
-
 #include "readline.h"
 
 int readline(char *s, int size)
@@ -22,7 +19,7 @@ int readline(char *s, int size)
 	c[1] = 0;
 	ptr = 0;
 	while(1) {
-		c[0] = readchar();
+		c[0] = getchar();
 		if (c[0] == skip)
 			continue;
 		skip = 0;
@@ -31,7 +28,7 @@ int readline(char *s, int size)
 			case 0x08:
 				if(ptr > 0) {
 					ptr--;
-					putsnonl("\x08 \x08");
+					fputs("\x08 \x08", stdout);
 				}
 				break;
 			case 0x07:
@@ -39,15 +36,15 @@ int readline(char *s, int size)
 			case '\r':
 				skip = '\n';
 				s[ptr] = 0x00;
-				putsnonl("\n");
+				fputs("\n", stdout);
 				return 0;
 			case '\n':
 				skip = '\r';
 				s[ptr] = 0x00;
-				putsnonl("\n");
+				fputs("\n", stdout);
 				return 0;
 			default:
-				putsnonl(c);
+				fputs(c, stdout);
 				s[ptr] = c[0];
 				ptr++;
 				break;

litex/soc/software/common.mak

@@ -14,7 +14,7 @@ else
 CC_normal      := $(TARGET_PREFIX)gcc -std=gnu99
 CX_normal      := $(TARGET_PREFIX)g++
 endif
-AR_normal      := $(TARGET_PREFIX)ar
+AR_normal      := $(TARGET_PREFIX)gcc-ar
 LD_normal      := $(TARGET_PREFIX)ld
 OBJCOPY_normal := $(TARGET_PREFIX)objcopy
 
@@ -45,15 +45,18 @@ DEPFLAGS += -MD -MP
 
 # Toolchain options
 #
-INCLUDES = -I$(SOC_DIRECTORY)/software/include/base \
+INCLUDES = -I$(PICOLIBC_DIRECTORY)/newlib/libc/tinystdio \
+           -I$(PICOLIBC_DIRECTORY)/newlib/libc/include \
+           -I$(LIBBASE_DIRECTORY) \
            -I$(SOC_DIRECTORY)/software/include \
            -I$(SOC_DIRECTORY)/software \
            -I$(BUILDINC_DIRECTORY) \
+           -I$(BUILDINC_DIRECTORY)/../libc \
            -I$(CPU_DIRECTORY)
-COMMONFLAGS = $(DEPFLAGS) -Os $(CPUFLAGS) -g3 -fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector $(INCLUDES)
+COMMONFLAGS = $(DEPFLAGS) -Os $(CPUFLAGS) -g3 -fomit-frame-pointer -Wall -fno-builtin -fno-stack-protector -flto $(INCLUDES)
 CFLAGS = $(COMMONFLAGS) -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes
 CXXFLAGS = $(COMMONFLAGS) -std=c++11 -I$(SOC_DIRECTORY)/software/include/basec++ -fexceptions -fno-rtti -ffreestanding
-LDFLAGS = -nostdlib -nodefaultlibs -L$(BUILDINC_DIRECTORY)
+LDFLAGS = -nostdlib -nodefaultlibs -Wl,--no-dynamic-linker -Wl,--build-id=none $(CFLAGS) -L$(BUILDINC_DIRECTORY)
 
 define compilexx
 $(CX) -c $(CXXFLAGS) $(1) $< -o $@

litex/soc/software/demo/Makefile

@@ -3,7 +3,7 @@ BUILD_DIR?=../build/
 include $(BUILD_DIR)/software/include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
-OBJECTS   = isr.o donut.o helloc.o main.o
+OBJECTS   = isr.o donut.o helloc.o main.o crt0.o
 ifdef WITH_CXX
 	OBJECTS += hellocpp.o
 endif
@@ -21,16 +21,17 @@ demo.elf: $(OBJECTS)
 	$(CC) $(LDFLAGS) \
 		-T linker.ld \
 		-N -o $@ \
-		$(BUILD_DIR)/software/libbase/crt0.o \
 		$(OBJECTS) \
-		-L$(BUILD_DIR)/software/libbase \
-		-L$(BUILD_DIR)/software/libcompiler_rt \
-		-lbase-nofloat -lcompiler_rt
+		$(PACKAGES:%=-L$(BUILD_DIR)/software/%) \
+		$(LIBS:lib%=-l%)
 	chmod -x $@
 
 main.o: main.c
 	$(compile)
 
+crt0.o: $(CPU_DIRECTORY)/crt0.S
+	$(assemble)
+
 donut.o: CFLAGS += -w
 
 helloc.o: CFLAGS += -w

litex/soc/software/demo/demo.py

@@ -8,7 +8,6 @@
 
 import os
 import argparse
-from distutils.dir_util import copy_tree
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX Bare Metal Demo App.")
@@ -20,8 +19,7 @@ def main():
     os.makedirs("demo", exist_ok=True)
 
     # Copy contents to demo directory
-    src = os.path.abspath(os.path.dirname(__file__))
-    copy_tree(src, "demo")
+    os.system(f"cp {os.path.abspath(os.path.dirname(__file__))}/* demo")
 
     # Compile demo
     build_path = args.build_path if os.path.isabs(args.build_path) else os.path.join("..", args.build_path)

litex/soc/software/demo/donut.c

@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include <console.h>
+#include <libbase/console.h>
 
 #define R(mul,shift,x,y) \
   _=x; \
@@ -59,9 +59,9 @@ void donut(void) {
     R(5, 7, cA, sA);
     R(5, 8, cB, sB);
   	if (readchar_nonblock()) {
-  		readchar();
+  		getchar();
   		break;
   	}
-    putsnonl("\x1b[23A");
+    fputs("\x1b[23A", stdout);
   }
-}
+}

litex/soc/software/demo/isr.c

@@ -4,7 +4,7 @@
 #include <generated/csr.h>
 #include <generated/soc.h>
 #include <irq.h>
-#include <uart.h>
+#include <libbase/uart.h>
 
 void isr(void);
 

litex/soc/software/demo/linker.ld

@@ -10,33 +10,41 @@ SECTIONS
 	.text :
 	{
 		_ftext = .;
+		/* Make sure crt0 files come first, and they, and the isr */
+		/* don't get disposed of by greedy optimisation */
+		*crt0*(.text)
+		KEEP(*crt0*(.text))
+		KEEP(*(.text.isr))
+
 		*(.text .stub .text.* .gnu.linkonce.t.*)
 		_etext = .;
 	} > main_ram
 
 	.rodata :
 	{
-		. = ALIGN(4);
+		. = ALIGN(8);
 		_frodata = .;
 		*(.rodata .rodata.* .gnu.linkonce.r.*)
 		*(.rodata1)
+		. = ALIGN(8);
 		_erodata = .;
 	} > main_ram
 
 	.data :
 	{
-		. = ALIGN(4);
+		. = ALIGN(8);
 		_fdata = .;
 		*(.data .data.* .gnu.linkonce.d.*)
 		*(.data1)
 		_gp = ALIGN(16);
 		*(.sdata .sdata.* .gnu.linkonce.s.*)
+		. = ALIGN(8);
 		_edata = .;
-	} > main_ram
+	} > sram AT > main_ram
 
 	.bss :
 	{
-		. = ALIGN(4);
+		. = ALIGN(8);
 		_fbss = .;
 		*(.dynsbss)
 		*(.sbss .sbss.* .gnu.linkonce.sb.*)
@@ -44,13 +52,13 @@ SECTIONS
 		*(.dynbss)
 		*(.bss .bss.* .gnu.linkonce.b.*)
 		*(COMMON)
-		. = ALIGN(4);
+		. = ALIGN(8);
 		_ebss = .;
 		_end = .;
 	} > sram
 }
 
-PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);
+PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram));
 
 PROVIDE(_fdata_rom = LOADADDR(.data));
 PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));

litex/soc/software/demo/main.c

@@ -6,8 +6,8 @@
 #include <string.h>
 
 #include <irq.h>
-#include <uart.h>
-#include <console.h>
+#include <libbase/uart.h>
+#include <libbase/console.h>
 #include <generated/csr.h>
 
 /*-----------------------------------------------------------------------*/
@@ -21,14 +21,14 @@ static char *readstr(void)
 	static int ptr = 0;
 
 	if(readchar_nonblock()) {
-		c[0] = readchar();
+		c[0] = getchar();
 		c[1] = 0;
 		switch(c[0]) {
 			case 0x7f:
 			case 0x08:
 				if(ptr > 0) {
 					ptr--;
-					putsnonl("\x08 \x08");
+					fputs("\x08 \x08", stdout);
 				}
 				break;
 			case 0x07:
@@ -36,13 +36,13 @@ static char *readstr(void)
 			case '\r':
 			case '\n':
 				s[ptr] = 0x00;
-				putsnonl("\n");
+				fputs("\n", stdout);
 				ptr = 0;
 				return s;
 			default:
 				if(ptr >= (sizeof(s) - 1))
 					break;
-				putsnonl(c);
+				fputs(c, stdout);
 				s[ptr] = c[0];
 				ptr++;
 				break;

litex/soc/software/include/base/assert.h

@@ -1,6 +0,0 @@
-#ifndef __ASSERT_H
-#define __ASSERT_H
-
-#define assert(x)
-
-#endif /* __ASSERT_H */

litex/soc/software/include/base/ctype.h

@@ -1,63 +0,0 @@
-#ifndef __CTYPE_H
-#define __CTYPE_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * NOTE! This ctype does not handle EOF like the standard C
- * library is required to.
- */
-
-#define _U	0x01	/* upper */
-#define _L	0x02	/* lower */
-#define _D	0x04	/* digit */
-#define _C	0x08	/* cntrl */
-#define _P	0x10	/* punct */
-#define _S	0x20	/* white space (space/lf/tab) */
-#define _X	0x40	/* hex digit */
-#define _SP	0x80	/* hard space (0x20) */
-
-extern const unsigned char _ctype[];
-
-#define __ismask(x) (_ctype[(int)(unsigned char)(x)])
-
-#define isalnum(c)	((__ismask(c)&(_U|_L|_D)) != 0)
-#define isalpha(c)	((__ismask(c)&(_U|_L)) != 0)
-#define iscntrl(c)	((__ismask(c)&(_C)) != 0)
-#define isdigit(c)	((__ismask(c)&(_D)) != 0)
-#define isgraph(c)	((__ismask(c)&(_P|_U|_L|_D)) != 0)
-#define islower(c)	((__ismask(c)&(_L)) != 0)
-#define isprint(c)	((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)
-#define ispunct(c)	((__ismask(c)&(_P)) != 0)
-/* Note: isspace() must return false for %NUL-terminator */
-#define isspace(c)	((__ismask(c)&(_S)) != 0)
-#define isupper(c)	((__ismask(c)&(_U)) != 0)
-#define isxdigit(c)	((__ismask(c)&(_D|_X)) != 0)
-
-#define isascii(c) (((unsigned char)(c))<=0x7f)
-#define toascii(c) (((unsigned char)(c))&0x7f)
-
-static inline unsigned char __tolower(unsigned char c)
-{
-	if (isupper(c))
-		c -= 'A'-'a';
-	return c;
-}
-
-static inline unsigned char __toupper(unsigned char c)
-{
-	if (islower(c))
-		c -= 'a'-'A';
-	return c;
-}
-
-#define tolower(c) __tolower(c)
-#define toupper(c) __toupper(c)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CTYPE_H */

litex/soc/software/include/base/div64.h

@@ -1,39 +0,0 @@
-#ifndef _ASM_GENERIC_DIV64_H
-#define _ASM_GENERIC_DIV64_H
-/*
- * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
- * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
- *
- * The semantics of do_div() are:
- *
- * uint32_t do_div(uint64_t *n, uint32_t base)
- * {
- * 	uint32_t remainder = *n % base;
- * 	*n = *n / base;
- * 	return remainder;
- * }
- *
- * NOTE: macro parameter n is evaluated multiple times,
- *       beware of side effects!
- */
-
-#include <stdint.h>
-
-extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
-
-/* The unnecessary pointer compare is there
- * to check for type safety (n must be 64bit)
- */
-# define do_div(n,base) ({				\
-	uint32_t __base = (base);			\
-	uint32_t __rem;					\
-	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
-	if (((n) >> 32) == 0) {			\
-		__rem = (uint32_t)(n) % __base;		\
-		(n) = (uint32_t)(n) / __base;		\
-	} else 						\
-		__rem = __div64_32(&(n), __base);	\
-	__rem;						\
- })
-
-#endif /* _ASM_GENERIC_DIV64_H */

litex/soc/software/include/base/endian.h

@@ -1,30 +0,0 @@
-#ifndef __ENDIAN_H
-#define __ENDIAN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define __LITTLE_ENDIAN 0
-#define __BIG_ENDIAN 1
-#define __BYTE_ORDER __BIG_ENDIAN
-
-static inline unsigned int le32toh(unsigned int val)
-{
-	return (val & 0xff) << 24 |
-		(val & 0xff00) << 8 |
-		(val & 0xff0000) >> 8 |
-		(val & 0xff000000) >> 24;
-}
-
-static inline unsigned short le16toh(unsigned short val)
-{
-	return (val & 0xff) << 8 |
-		(val & 0xff00) >> 8;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ENDIAN_H */

litex/soc/software/include/base/errno.h

@@ -1,261 +0,0 @@
-#ifndef __ERRNO_H
-#define __ERRNO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern int errno;
-
-#define EPERM               1
-#define EPERM_STR           "Operation not permitted"
-#define ENOENT              2
-#define ENOENT_STR          "No such file or directory"
-#define ESRCH               3
-#define ESRCH_STR           "No such process"
-#define EINTR               4
-#define EINTR_STR           "Interrupted system call"
-#define EIO                 5
-#define EIO_STR             "I/O error"
-#define ENXIO               6
-#define ENXIO_STR           "No such device or address"
-#define E2BIG               7
-#define E2BIG_STR           "Arg list too long"
-#define ENOEXEC             8
-#define ENOEXEC_STR         "Exec format error"
-#define EBADF               9
-#define EBADF_STR           "Bad file number"
-#define ECHILD              10
-#define ECHILD_STR          "No child processes"
-#define EAGAIN              11
-#define EWOULDBLOCK         EAGAIN
-#define EAGAIN_STR          "Try again"
-#define ENOMEM              12
-#define ENOMEM_STR          "Out of memory"
-#define EACCES              13
-#define EACCES_STR          "Permission denied"
-#define EFAULT              14
-#define EFAULT_STR          "Bad address"
-#define ENOTBLK             15
-#define ENOTBLK_STR         "Block device required"
-#define EBUSY               16
-#define EBUSY_STR           "Device or resource busy"
-#define EEXIST              17
-#define EEXIST_STR          "File exists"
-#define EXDEV               18
-#define EXDEV_STR           "Cross-device link"
-#define ENODEV              19
-#define ENODEV_STR          "No such device"
-#define ENOTDIR             20
-#define ENOTDIR_STR         "Not a directory"
-#define EISDIR              21
-#define EISDIR_STR          "Is a directory"
-#define EINVAL              22
-#define EINVAL_STR          "Invalid argument"
-#define ENFILE              23
-#define ENFILE_STR          "File table overflow"
-#define EMFILE              24
-#define EMFILE_STR          "Too many open files"
-#define ENOTTY              25
-#define ENOTTY_STR          "Not a typewriter"
-#define ETXTBSY             26
-#define ETXTBSY_STR         "Text file busy"
-#define EFBIG               27
-#define EFBIG_STR           "File too large"
-#define ENOSPC              28
-#define ENOSPC_STR          "No space left on device"
-#define ESPIPE              29
-#define ESPIPE_STR          "Illegal seek"
-#define EROFS               30
-#define EROFS_STR           "Read-only file system"
-#define EMLINK              31
-#define EMLINK_STR          "Too many links"
-#define EPIPE               32
-#define EPIPE_STR           "Broken pipe"
-#define EDOM                33
-#define EDOM_STR            "Math argument out of domain of func"
-#define ERANGE              34
-#define ERANGE_STR          "Math result not representable"
-#define EDEADLK             35
-#define EDEADLOCK           EDEADLK
-#define EDEADLK_STR         "Resource deadlock would occur"
-#define ENAMETOOLONG        36
-#define ENAMETOOLONG_STR    "File name too long"
-#define ENOLCK              37
-#define ENOLCK_STR          "No record locks available"
-#define ENOSYS              38
-#define ENOSYS_STR          "Function not implemented"
-#define ENOTEMPTY           39
-#define ENOTEMPTY_STR       "Directory not empty"
-#define ELOOP               40
-#define ELOOP_STR           "Too many symbolic links encountered"
-#define ENOMSG              42
-#define ENOMSG_STR          "No message of desired type"
-#define EIDRM               43
-#define EIDRM_STR           "Identifier removed"
-#define ECHRNG              44
-#define ECHRNG_STR          "Channel number out of range"
-#define EL2NSYNC            45
-#define EL2NSYNC_STR        "Level 2 not synchronized"
-#define EL3HLT              46
-#define EL3HLT_STR          "Level 3 halted"
-#define EL3RST              47
-#define EL3RST_STR          "Level 3 reset"
-#define ELNRNG              48
-#define ELNRNG_STR          "Link number out of range"
-#define EUNATCH             49
-#define EUNATCH_STR         "Protocol driver not attached"
-#define ENOCSI              50
-#define ENOCSI_STR          "No CSI structure available"
-#define EL2HLT              51
-#define EL2HLT_STR          "Level 2 halted"
-#define EBADE               52
-#define EBADE_STR           "Invalid exchange"
-#define EBADR               53
-#define EBADR_STR           "Invalid request descriptor"
-#define EXFULL              54
-#define EXFULL_STR          "Exchange full"
-#define ENOANO              55
-#define ENOANO_STR          "No anode"
-#define EBADRQC             56
-#define EBADRQC_STR         "Invalid request code"
-#define EBADSLT             57
-#define EBADSLT_STR         "Invalid slot"
-#define EBFONT              59
-#define EBFONT_STR          "Bad font file format"
-#define ENOSTR              60
-#define ENOSTR_STR          "Device not a stream"
-#define ENODATA             61
-#define ENODATA_STR         "No data available"
-#define ETIME               62
-#define ETIME_STR           "Timer expired"
-#define ENOSR               63
-#define ENOSR_STR           "Out of streams resources"
-#define ENONET              64
-#define ENONET_STR          "Machine is not on the network"
-#define ENOPKG              65
-#define ENOPKG_STR          "Package not installed"
-#define EREMOTE             66
-#define EREMOTE_STR         "Object is remote"
-#define ENOLINK             67
-#define ENOLINK_STR         "Link has been severed"
-#define EADV                68
-#define EADV_STR            "Advertise error"
-#define ESRMNT              69
-#define ESRMNT_STR          "Srmount error"
-#define ECOMM               70
-#define ECOMM_STR           "Communication error on send"
-#define EPROTO              71
-#define EPROTO_STR          "Protocol error"
-#define EMULTIHOP           72
-#define EMULTIHOP_STR       "Multihop attempted"
-#define EDOTDOT             73
-#define EDOTDOT_STR         "RFS specific error"
-#define EBADMSG             74
-#define EBADMSG_STR         "Not a data message"
-#define EOVERFLOW           75
-#define EOVERFLOW_STR       "Value too large for defined data type"
-#define ENOTUNIQ            76
-#define ENOTUNIQ_STR        "Name not unique on network"
-#define EBADFD              77
-#define EBADFD_STR          "File descriptor in bad state"
-#define EREMCHG             78
-#define EREMCHG_STR         "Remote address changed"
-#define ELIBACC             79
-#define ELIBACC_STR         "Can not access a needed shared library"
-#define ELIBBAD             80
-#define ELIBBAD_STR         "Accessing a corrupted shared library"
-#define ELIBSCN             81
-#define ELIBSCN_STR         ".lib section in a.out corrupted"
-#define ELIBMAX             82
-#define ELIBMAX_STR         "Attempting to link in too many shared libraries"
-#define ELIBEXEC            83
-#define ELIBEXEC_STR        "Cannot exec a shared library directly"
-#define EILSEQ              84
-#define EILSEQ_STR          "Illegal byte sequence"
-#define ERESTART            85
-#define ERESTART_STR        "Interrupted system call should be restarted"
-#define ESTRPIPE            86
-#define ESTRPIPE_STR        "Streams pipe error"
-#define EUSERS              87
-#define EUSERS_STR          "Too many users"
-#define ENOTSOCK            88
-#define ENOTSOCK_STR        "Socket operation on non-socket"
-#define EDESTADDRREQ        89
-#define EDESTADDRREQ_STR    "Destination address required"
-#define EMSGSIZE            90
-#define EMSGSIZE_STR        "Message too long"
-#define EPROTOTYPE          91
-#define EPROTOTYPE_STR      "Protocol wrong type for socket"
-#define ENOPROTOOPT         92
-#define ENOPROTOOPT_STR     "Protocol not available"
-#define EPROTONOSUPPORT      93
-#define EPROTONOSUPPORT_STR "Protocol not supported"
-#define ESOCKTNOSUPPORT     94
-#define ESOCKTNOSUPPORT_STR "Socket type not supported"
-#define EOPNOTSUPP          95
-#define EOPNOTSUPP_STR      "Operation not supported on transport endpoint"
-#define EPFNOSUPPORT        96
-#define EPFNOSUPPORT_STR    "Protocol family not supported"
-#define EAFNOSUPPORT        97
-#define EAFNOSUPPORT_STR    "Address family not supported by protocol"
-#define EADDRINUSE          98
-#define EADDRINUSE_STR      "Address already in use"
-#define EADDRNOTAVAIL       99
-#define EADDRNOTAVAIL_STR   "Cannot assign requested address"
-#define ENETDOWN            100
-#define ENETDOWN_STR        "Network is down"
-#define ENETUNREACH         101
-#define ENETUNREACH_STR     "Network is unreachable"
-#define ENETRESET           102
-#define ENETRESET_STR       "Network dropped connection because of reset"
-#define ECONNABORTED        103
-#define ECONNABORTED_STR    "Software caused connection abort"
-#define ECONNRESET          104
-#define ECONNRESET_STR      "Connection reset by peer"
-#define ENOBUFS             105
-#define ENOBUFS_STR         "No buffer space available"
-#define EISCONN             106
-#define EISCONN_STR         "Transport endpoint is already connected"
-#define ENOTCONN            107
-#define ENOTCONN_STR        "Transport endpoint is not connected"
-#define ESHUTDOWN           108
-#define ESHUTDOWN_STR       "Cannot send after transport endpoint shutdown"
-#define ETOOMANYREFS        109
-#define ETOOMANYREFS_STR    "Too many references: cannot splice"
-#define ETIMEDOUT           110
-#define ETIMEDOUT_STR       "Connection timed out"
-#define ECONNREFUSED        111
-#define ECONNREFUSED_STR    "Connection refused"
-#define EHOSTDOWN           112
-#define EHOSTDOWN_STR       "Host is down"
-#define EHOSTUNREACH        113
-#define EHOSTUNREACH_STR    "No route to host"
-#define EALREADY            114
-#define EALREADY_STR        "Operation already in progress"
-#define EINPROGRESS         115
-#define EINPROGRESS_STR     "Operation now in progress"
-#define ESTALE              116
-#define ESTALE_STR          "Stale NFS file handle"
-#define EUCLEAN             117
-#define EUCLEAN_STR         "Structure needs cleaning"
-#define ENOTNAM             118
-#define ENOTNAM_STR         "Not a XENIX named type file"
-#define ENAVAIL             119
-#define ENAVAIL_STR         "No XENIX semaphores available"
-#define EISNAM              120
-#define EISNAM_STR          "Is a named type file"
-#define EREMOTEIO           121
-#define EREMOTEIO_STR       "Remote I/O error"
-#define EDQUOT              122
-#define EDQUOT_STR          "Quota exceeded"
-#define ENOMEDIUM           123
-#define ENOMEDIUM_STR       "No medium found"
-#define EMEDIUMTYPE         124
-#define EMEDIUMTYPE_STR     "Wrong medium type"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ERRNO_H */

litex/soc/software/include/base/float.h

@@ -1,58 +0,0 @@
-#ifndef __FLOAT_H
-#define __FLOAT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define FLT_EVAL_METHOD __FLT_EVAL_METHOD__
-#define FLT_ROUNDS (__builtin_flt_rounds())
-#define FLT_RADIX __FLT_RADIX__
-
-#define FLT_MANT_DIG __FLT_MANT_DIG__
-#define DBL_MANT_DIG __DBL_MANT_DIG__
-#define LDBL_MANT_DIG __LDBL_MANT_DIG__
-
-#define DECIMAL_DIG __DECIMAL_DIG__
-
-#define FLT_DIG __FLT_DIG__
-#define DBL_DIG __DBL_DIG__
-#define LDBL_DIG __LDBL_DIG__
-
-#define FLT_MIN_EXP __FLT_MIN_EXP__
-#define DBL_MIN_EXP __DBL_MIN_EXP__
-#define LDBL_MIN_EXP __LDBL_MIN_EXP__
-
-#define FLT_MIN_10_EXP __FLT_MIN_10_EXP__
-#define DBL_MIN_10_EXP __DBL_MIN_10_EXP__
-#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__
-
-#define FLT_MAX_EXP __FLT_MAX_EXP__
-#define DBL_MAX_EXP __DBL_MAX_EXP__
-#define LDBL_MAX_EXP __LDBL_MAX_EXP__
-
-#define FLT_MAX_10_EXP __FLT_MAX_10_EXP__
-#define DBL_MAX_10_EXP __DBL_MAX_10_EXP__
-#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__
-
-#define FLT_MAX __FLT_MAX__
-#define DBL_MAX __DBL_MAX__
-#define LDBL_MAX __LDBL_MAX__
-
-#define FLT_EPSILON __FLT_EPSILON__
-#define DBL_EPSILON __DBL_EPSILON__
-#define LDBL_EPSILON __LDBL_EPSILON__
-
-#define FLT_MIN __FLT_MIN__
-#define DBL_MIN __DBL_MIN__
-#define LDBL_MIN __LDBL_MIN__
-
-#define FLT_TRUE_MIN __FLT_DENORM_MIN__
-#define DBL_TRUE_MIN __DBL_DENORM_MIN__
-#define LDBL_TRUE_MIN __LDBL_DENORM_MIN__
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __FLOAT_H */

litex/soc/software/include/base/id.h

@@ -1,15 +0,0 @@
-#ifndef __ID_H
-#define __ID_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define IDENT_SIZE 256
-void get_ident(char *ident);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ID_H */

litex/soc/software/include/base/inet.h

@@ -1,52 +0,0 @@
-/* Copyright © 2005-2014 Rich Felker, et al.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __INET_H
-#define __INET_H
-
-#include <stdint.h>
-
-static __inline uint16_t __bswap_16(uint16_t __x)
-{
-	return (__x<<8) | (__x>>8);
-}
-
-static __inline uint32_t __bswap_32(uint32_t __x)
-{
-	return (__x>>24) | ((__x>>8)&0xff00) | ((__x<<8)&0xff0000) | (__x<<24);
-}
-
-static __inline uint64_t __bswap_64(uint64_t __x)
-{
-	return (__bswap_32(__x)+(0ULL<<32)) | __bswap_32(__x>>32);
-}
-
-#define bswap_16(x) __bswap_16(x)
-#define bswap_32(x) __bswap_32(x)
-#define bswap_64(x) __bswap_64(x)
-
-uint16_t htons(uint16_t n);
-uint32_t htonl(uint32_t n);
-uint16_t ntohs(uint16_t n);
-uint32_t ntohl(uint32_t n);
-
-#endif /* __INET_H */

litex/soc/software/include/base/inttypes.h

@@ -1,231 +0,0 @@
-/* Copyright (C) 1997-2014 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
-
-   The GNU C Library is free software; you can redistribute it and/or
-   modify it under the terms of the GNU Lesser General Public
-   License as published by the Free Software Foundation; either
-   version 2.1 of the License, or (at your option) any later version.
-
-   The GNU C Library is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   Lesser General Public License for more details.
-
-   You should have received a copy of the GNU Lesser General Public
-   License along with the GNU C Library; if not, see
-   <http://www.gnu.org/licenses/>.  */
-
-/*
- *      ISO C99: 7.8 Format conversion of integer types <inttypes.h>
- */
-
-#ifndef __INTTYPES_H
-#define __INTTYPES_H
-
-#include <stdint.h>
-
-# ifdef __LP64__
-#  define __PRI64_PREFIX        "l"
-#  define __PRIPTR_PREFIX       "l"
-# else
-#  define __PRI64_PREFIX        "ll"
-#  define __PRIPTR_PREFIX
-# endif
-
-/* Macros for printing format specifiers.  */
-
-/* Decimal notation.  */
-# define PRId8          "d"
-# define PRId16         "d"
-# define PRId32         "d"
-# define PRId64         __PRI64_PREFIX "d"
-
-# define PRIdLEAST8     "d"
-# define PRIdLEAST16    "d"
-# define PRIdLEAST32    "d"
-# define PRIdLEAST64    __PRI64_PREFIX "d"
-
-# define PRIdFAST8      "d"
-# define PRIdFAST16     __PRIPTR_PREFIX "d"
-# define PRIdFAST32     __PRIPTR_PREFIX "d"
-# define PRIdFAST64     __PRI64_PREFIX "d"
-
-
-# define PRIi8          "i"
-# define PRIi16         "i"
-# define PRIi32         "i"
-# define PRIi64         __PRI64_PREFIX "i"
-
-# define PRIiLEAST8     "i"
-# define PRIiLEAST16    "i"
-# define PRIiLEAST32    "i"
-# define PRIiLEAST64    __PRI64_PREFIX "i"
-
-# define PRIiFAST8      "i"
-# define PRIiFAST16     __PRIPTR_PREFIX "i"
-# define PRIiFAST32     __PRIPTR_PREFIX "i"
-# define PRIiFAST64     __PRI64_PREFIX "i"
-
-/* Octal notation.  */
-# define PRIo8          "o"
-# define PRIo16         "o"
-# define PRIo32         "o"
-# define PRIo64         __PRI64_PREFIX "o"
-
-# define PRIoLEAST8     "o"
-# define PRIoLEAST16    "o"
-# define PRIoLEAST32    "o"
-# define PRIoLEAST64    __PRI64_PREFIX "o"
-
-# define PRIoFAST8      "o"
-# define PRIoFAST16     __PRIPTR_PREFIX "o"
-# define PRIoFAST32     __PRIPTR_PREFIX "o"
-# define PRIoFAST64     __PRI64_PREFIX "o"
-
-/* Unsigned integers.  */
-# define PRIu8          "u"
-# define PRIu16         "u"
-# define PRIu32         "u"
-# define PRIu64         __PRI64_PREFIX "u"
-
-# define PRIuLEAST8     "u"
-# define PRIuLEAST16    "u"
-# define PRIuLEAST32    "u"
-# define PRIuLEAST64    __PRI64_PREFIX "u"
-
-# define PRIuFAST8      "u"
-# define PRIuFAST16     __PRIPTR_PREFIX "u"
-# define PRIuFAST32     __PRIPTR_PREFIX "u"
-# define PRIuFAST64     __PRI64_PREFIX "u"
-
-/* lowercase hexadecimal notation.  */
-# define PRIx8          "x"
-# define PRIx16         "x"
-# define PRIx32         "x"
-# define PRIx64         __PRI64_PREFIX "x"
-
-# define PRIxLEAST8     "x"
-# define PRIxLEAST16    "x"
-# define PRIxLEAST32    "x"
-# define PRIxLEAST64    __PRI64_PREFIX "x"
-
-# define PRIxFAST8      "x"
-# define PRIxFAST16     __PRIPTR_PREFIX "x"
-# define PRIxFAST32     __PRIPTR_PREFIX "x"
-# define PRIxFAST64     __PRI64_PREFIX "x"
-
-/* UPPERCASE hexadecimal notation.  */
-# define PRIX8          "X"
-# define PRIX16         "X"
-# define PRIX32         "X"
-# define PRIX64         __PRI64_PREFIX "X"
-
-# define PRIXLEAST8     "X"
-# define PRIXLEAST16    "X"
-# define PRIXLEAST32    "X"
-# define PRIXLEAST64    __PRI64_PREFIX "X"
-
-# define PRIXFAST8      "X"
-# define PRIXFAST16     __PRIPTR_PREFIX "X"
-# define PRIXFAST32     __PRIPTR_PREFIX "X"
-# define PRIXFAST64     __PRI64_PREFIX "X"
-
-/* Macros for printing `intmax_t' and `uintmax_t'.  */
-# define PRIdMAX        __PRI64_PREFIX "d"
-# define PRIiMAX        __PRI64_PREFIX "i"
-# define PRIoMAX        __PRI64_PREFIX "o"
-# define PRIuMAX        __PRI64_PREFIX "u"
-# define PRIxMAX        __PRI64_PREFIX "x"
-# define PRIXMAX        __PRI64_PREFIX "X"
-
-
-/* Macros for printing `intptr_t' and `uintptr_t'.  */
-# define PRIdPTR        __PRIPTR_PREFIX "d"
-# define PRIiPTR        __PRIPTR_PREFIX "i"
-# define PRIoPTR        __PRIPTR_PREFIX "o"
-# define PRIuPTR        __PRIPTR_PREFIX "u"
-# define PRIxPTR        __PRIPTR_PREFIX "x"
-# define PRIXPTR        __PRIPTR_PREFIX "X"
-
-/* Macros for scanning format specifiers.  */
-
-/* Signed decimal notation.  */
-# define SCNd8          "hhd"
-# define SCNd16         "hd"
-# define SCNd32         "d"
-# define SCNd64         __PRI64_PREFIX "d"
-
-# define SCNdLEAST8     "hhd"
-# define SCNdLEAST16    "hd"
-# define SCNdLEAST32    "d"
-# define SCNdLEAST64    __PRI64_PREFIX "d"
-
-# define SCNdFAST8      "hhd"
-# define SCNdFAST16     __PRIPTR_PREFIX "d"
-# define SCNdFAST32     __PRIPTR_PREFIX "d"
-# define SCNdFAST64     __PRI64_PREFIX "d"
-
-/* Unsigned decimal notation.  */
-# define SCNu8          "hhu"
-# define SCNu16         "hu"
-# define SCNu32         "u"
-# define SCNu64         __PRI64_PREFIX "u"
-
-# define SCNuLEAST8     "hhu"
-# define SCNuLEAST16    "hu"
-# define SCNuLEAST32    "u"
-# define SCNuLEAST64    __PRI64_PREFIX "u"
-
-# define SCNuFAST8      "hhu"
-# define SCNuFAST16     __PRIPTR_PREFIX "u"
-# define SCNuFAST32     __PRIPTR_PREFIX "u"
-# define SCNuFAST64     __PRI64_PREFIX "u"
-
-/* Octal notation.  */
-# define SCNo8          "hho"
-# define SCNo16         "ho"
-# define SCNo32         "o"
-# define SCNo64         __PRI64_PREFIX "o"
-
-# define SCNoLEAST8     "hho"
-# define SCNoLEAST16    "ho"
-# define SCNoLEAST32    "o"
-# define SCNoLEAST64    __PRI64_PREFIX "o"
-
-# define SCNoFAST8      "hho"
-# define SCNoFAST16     __PRIPTR_PREFIX "o"
-# define SCNoFAST32     __PRIPTR_PREFIX "o"
-# define SCNoFAST64     __PRI64_PREFIX "o"
-
-/* Hexadecimal notation.  */
-# define SCNx8          "hhx"
-# define SCNx16         "hx"
-# define SCNx32         "x"
-# define SCNx64         __PRI64_PREFIX "x"
-
-# define SCNxLEAST8     "hhx"
-# define SCNxLEAST16    "hx"
-# define SCNxLEAST32    "x"
-# define SCNxLEAST64    __PRI64_PREFIX "x"
-
-# define SCNxFAST8      "hhx"
-# define SCNxFAST16     __PRIPTR_PREFIX "x"
-# define SCNxFAST32     __PRIPTR_PREFIX "x"
-# define SCNxFAST64     __PRI64_PREFIX "x"
-
-
-/* Macros for scanning `intmax_t' and `uintmax_t'.  */
-# define SCNdMAX        __PRI64_PREFIX "d"
-# define SCNiMAX        __PRI64_PREFIX "i"
-# define SCNoMAX        __PRI64_PREFIX "o"
-# define SCNuMAX        __PRI64_PREFIX "u"
-# define SCNxMAX        __PRI64_PREFIX "x"
-
-/* Macros for scaning `intptr_t' and `uintptr_t'.  */
-# define SCNdPTR        __PRIPTR_PREFIX "d"
-# define SCNiPTR        __PRIPTR_PREFIX "i"
-# define SCNoPTR        __PRIPTR_PREFIX "o"
-# define SCNuPTR        __PRIPTR_PREFIX "u"
-# define SCNxPTR        __PRIPTR_PREFIX "x"
-
-#endif /* __INTTYPES_H */

litex/soc/software/include/base/limits.h

@@ -1,30 +0,0 @@
-#ifndef __LIMITS_H
-#define __LIMITS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __LP64__
-#define ULONG_MAX	18446744073709551615UL
-#else
-#define ULONG_MAX	4294967295UL
-#endif
-
-#define UINT_MAX	4294967295U
-#define INT_MIN		(-INT_MAX - 1)
-#define INT_MAX		2147483647
-
-#define USHRT_MAX	65535
-#define SHRT_MIN	(-32768)
-#define SHRT_MAX	32767
-
-#define UCHAR_MAX	255
-
-#define CHAR_BIT 8
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LIMITS_H */

litex/soc/software/include/base/math.h

@@ -1,14 +0,0 @@
-#ifndef __MATH_H
-#define __MATH_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "../fdlibm/fdlibm.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MATH_H */

litex/soc/software/include/base/pthread.h

@@ -1,27 +0,0 @@
-#ifndef __PTHREAD_H
-#define __PTHREAD_H
-
-typedef int pthread_rwlock_t;
-
-#define PTHREAD_RWLOCK_INITIALIZER 0
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-inline int pthread_rwlock_rdlock(pthread_rwlock_t *rwlock)
-  { return 0; }
-inline int pthread_rwlock_tryrdlock(pthread_rwlock_t *rwlock)
-  { return 0; }
-inline int pthread_rwlock_wrlock(pthread_rwlock_t *rwlock)
-  { return 0; }
-inline int pthread_rwlock_trywrlock(pthread_rwlock_t *rwlock)
-  { return 0; }
-int pthread_rwlock_unlock(pthread_rwlock_t *rwlock)
-  { return 0; }
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __PTHREAD_H */

litex/soc/software/include/base/stdarg.h

@@ -1,25 +0,0 @@
-#ifndef __STDARG_H
-#define __STDARG_H
-
-#include <stdlib.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define va_start(v, l) __builtin_va_start((v), l)
-#define va_arg(ap, type) __builtin_va_arg((ap), type)
-#define va_copy(aq, ap) __builtin_va_copy((aq), (ap))
-#define va_end(ap) __builtin_va_end(ap)
-#define va_list __builtin_va_list
-
-int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
-int vscnprintf(char *buf, size_t size, const char *fmt, va_list args);
-int vsprintf(char *buf, const char *fmt, va_list args);
-int vprintf(const char *format, va_list ap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STDARG_H */

litex/soc/software/include/base/stdbool.h

@@ -1,8 +0,0 @@
-#ifndef __STDBOOL_H
-#define __STDBOOL_H
-
-#define bool _Bool
-#define true 1
-#define false 0
-
-#endif /* __STDBOOL_H */

litex/soc/software/include/base/stddef.h

@@ -1,28 +0,0 @@
-#ifndef __STDDEF_H
-#define __STDDEF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-#define NULL 0
-#else
-#define NULL ((void *)0)
-#endif
-
-#ifdef __LP64__
-typedef unsigned long size_t;
-typedef long ptrdiff_t;
-#else
-typedef unsigned int size_t;
-typedef int ptrdiff_t;
-#endif
-
-#define offsetof(type, member) __builtin_offsetof(type, member)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STDDEF_H */

litex/soc/software/include/base/stdint.h

@@ -1,63 +0,0 @@
-#ifndef __STDINT_H
-#define __STDINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __LP64__
-typedef long intptr_t;
-typedef unsigned long uintptr_t;
-#else
-typedef int intptr_t;
-typedef unsigned int uintptr_t;
-#endif
-
-typedef unsigned long long uint64_t;
-typedef unsigned int uint32_t;
-typedef unsigned short uint16_t;
-typedef unsigned char uint8_t;
-
-typedef long long int64_t;
-typedef int int32_t;
-typedef short int16_t;
-typedef signed char int8_t;
-
-typedef signed char int_least8_t;
-typedef unsigned char uint_least8_t;
-typedef signed short int_least16_t;
-typedef unsigned short uint_least16_t;
-typedef signed int int_least32_t;
-typedef unsigned int uint_least32_t;
-typedef signed long long int_least64_t;
-typedef unsigned long long uint_least64_t;
-
-#define INT8_MAX 127
-#define INT16_MAX 32767
-#define INT32_MAX 2147483647
-#define INT64_MAX 9223372036854775807LL
-
-#define INT8_MIN -128
-#define INT16_MIN -32768
-#define INT32_MIN (-INT32_MAX - 1)
-#define INT64_MIN (-INT64_MAX - 1LL)
-
-#define UINT8_MAX 255
-#define UINT16_MAX 65535
-#define UINT32_MAX 4294967295U
-#define UINT64_MAX 18446744073709551615ULL
-
-#define __int_c_join(a, b) a ## b
-#define __int_c(v, suffix) __int_c_join(v, suffix)
-#define __uint_c(v, suffix) __int_c_join(v##U, suffix)
-
-#define INT64_C(v) __int_c(v, LL)
-#define UINT64_C(v) __uint_c(v, LL)
-#define INT32_C(v) v
-#define UINT32_C(v) v##U
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STDINT_H */

litex/soc/software/include/base/stdio.h

@@ -1,77 +0,0 @@
-#ifndef __STDIO_H
-#define __STDIO_H
-
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int putchar(int c);
-int puts(const char *s);
-
-int snprintf(char *buf, size_t size, const char *fmt, ...) __attribute__((format(printf, 3, 4)));
-int scnprintf(char *buf, size_t size, const char *fmt, ...) __attribute__((format(printf, 3, 4)));
-int sprintf(char *buf, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-
-int printf(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
-
-/* Not sure this belongs here... */
-typedef long long loff_t;
-typedef long off_t;
-typedef int mode_t;
-typedef int dev_t;
-
-/*
- * Note: this library does not provide FILE operations.
- * User code must implement them.
- */
-
-#ifndef BUFSIZ
-#define BUFSIZ 1024
-#endif
-
-#ifndef EOF
-#define EOF -1
-#endif
-
-#ifndef SEEK_SET
-#define SEEK_SET	0
-#endif
-
-#ifndef SEEK_CUR
-#define SEEK_CUR	1
-#endif
-
-#ifndef SEEK_END
-#define SEEK_END	2
-#endif
-
-typedef int FILE;
-
-extern FILE *stdin;
-extern FILE *stdout;
-extern FILE *stderr;
-
-int fprintf(FILE *stream, const char *format, ...) __attribute__((format(printf, 2, 3)));
-int fflush(FILE *stream);
-
-FILE *fopen(const char *path, const char *mode);
-FILE *freopen(const char *path, const char *mode, FILE *stream);
-char *fgets(char *s, int size, FILE *stream);
-size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream);
-size_t fwrite(const void *ptr, size_t size, size_t nmemb, FILE *stream);
-int getc(FILE *stream);
-int fputc(int c, FILE *stream);
-int ferror(FILE *stream);
-int feof(FILE *stream);
-int fclose(FILE *fp);
-
-int fseek(FILE *stream, long offset, int whence);
-long ftell(FILE *stream);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STDIO_H */

litex/soc/software/include/base/stdlib.h

@@ -1,85 +0,0 @@
-/*
- * MiSoC
- * Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
- * Copyright (C) Linux kernel developers
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __STDLIB_H
-#define __STDLIB_H
-
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define PRINTF_ZEROPAD	1		/* pad with zero */
-#define PRINTF_SIGN	2		/* unsigned/signed long */
-#define PRINTF_PLUS	4		/* show plus */
-#define PRINTF_SPACE	8		/* space if plus */
-#define PRINTF_LEFT	16		/* left justified */
-#define PRINTF_SPECIAL	32		/* 0x */
-#define PRINTF_LARGE	64		/* use 'ABCDEF' instead of 'abcdef' */
-
-#define likely(x) x
-#define unlikely(x) x
-
-static inline int abs(int x)
-{
-	return x > 0 ? x : -x;
-}
-
-static inline long int labs(long int x)
-{
-	return x > 0 ? x : -x;
-}
-
-unsigned long strtoul(const char *nptr, char **endptr, unsigned int base);
-long strtol(const char *nptr, char **endptr, int base);
-double strtod(const char *str, char **endptr);
-
-int skip_atoi(const char **s);
-static inline int atoi(const char *nptr) {
-	return strtol(nptr, NULL, 10);
-}
-static inline long atol(const char *nptr) {
-	return (long)atoi(nptr);
-}
-char *number(char *buf, char *end, unsigned long num, int base, int size, int precision, int type);
-
-#define   RAND_MAX        2147483647
-
-unsigned int rand(void);
-void srand(unsigned int seed);
-void abort(void) __attribute__((noreturn));
-
-void qsort(void *base, size_t nmemb, size_t size, int(*compar)(const void *, const void *));
-
-/*
- * The following functions are not provided by this library.
- */
-
-char *getenv(const char *name);
-
-void *malloc(size_t size);
-void *calloc(size_t nmemb, size_t size);
-void free(void *ptr);
-void *realloc(void *ptr, size_t size);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STDLIB_H */

litex/soc/software/include/base/string.h

@@ -1,55 +0,0 @@
-/*
- * MiSoC
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
- * Copyright (C) Linus Torvalds and Linux kernel developers
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __STRING_H
-#define __STRING_H
-
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-char *strchr(const char *s, int c);
-char *strpbrk(const char *,const char *);
-char *strrchr(const char *s, int c);
-char *strnchr(const char *s, size_t count, int c);
-char *strcpy(char *dest, const char *src);
-char *strncpy(char *dest, const char *src, size_t count);
-int strcmp(const char *cs, const char *ct);
-int strncmp(const char *cs, const char *ct, size_t count);
-int strcasecmp(const char *cs, const char *ct);
-char *strcat(char *dest, const char *src);
-char *strncat(char *dest, const char *src, size_t n);
-size_t strlen(const char *s);
-size_t strnlen(const char *s, size_t count);
-size_t strspn(const char *s, const char *accept);
-int memcmp(const void *cs, const void *ct, size_t count);
-void *memset(void *s, int c, size_t count);
-void *memcpy(void *to, const void *from, size_t n);
-void *memmove(void *dest, const void *src, size_t count);
-char *strstr(const char *s1, const char *s2);
-void *memchr(const void *s, int c, size_t n);
-
-char *strerror(int errnum);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STRING_H */

litex/soc/software/include/base/time.h

@@ -1,15 +0,0 @@
-#ifndef __TIME_H
-#define __TIME_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void time_init(void);
-int elapsed(int *last_event, int period);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __TIME_H */

litex/soc/software/include/basec++/algorithm

@@ -1,4 +0,0 @@
-#ifndef __CXX_ALGORITHM
-#define __CXX_ALGORITHM
-
-#endif /* __CXX_ALGORITHM */

litex/soc/software/include/basec++/cstddef

@@ -1,11 +0,0 @@
-#ifndef __CXX_CSTDDEF
-#define __CXX_CSTDDEF
-
-#include <stddef.h>
-
-namespace std {
-  using ::size_t;
-  using ::ptrdiff_t;
-}
-
-#endif /* __CXX_CSTDDEF */

litex/soc/software/include/basec++/cstdlib

@@ -1,6 +0,0 @@
-#ifndef __CXX_CSTDLIB
-#define __CXX_CSTDLIB
-
-#include <stdlib.h>
-
-#endif /* __CXX_CSTDLIB */

litex/soc/software/include/basec++/new

@@ -1,9 +0,0 @@
-#ifndef __CXX_NEW
-#define __CXX_NEW
-
-#include <cstddef>
-
-inline void* operator new (std::size_t size, void* ptr) noexcept
-  { return ptr; }
-
-#endif /* __CXX_NEW */

litex/soc/software/include/dyld/dlfcn.h

@@ -1,28 +0,0 @@
-#ifndef __DLFCN_H
-#define __DLFCN_H
-
-typedef struct
-{
-  const char *dli_fname;        /* File name of defining object.  */
-  void *dli_fbase;              /* Load address of that object.  */
-  const char *dli_sname;        /* Name of nearest symbol.  */
-  void *dli_saddr;              /* Exact value of nearest symbol.  */
-} Dl_info;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern int dl_iterate_phdr (int (*__callback) (struct dl_phdr_info *,
-                                               size_t, void *),
-                            void *__data);
-
-/* Fill in *INFO with the following information about ADDRESS.
-   Returns 0 iff no shared object's segments contain that address.  */
-extern int dladdr (const void *__address, Dl_info *__info);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DLFCN_H */

litex/soc/software/include/dyld/dyld.h

@@ -1,31 +0,0 @@
-#ifndef __DYLD_H
-#define __DYLD_H
-
-#include <elf.h>
-
-struct dyld_info {
-    Elf32_Addr base;
-    const char *strtab;
-    const Elf32_Sym *symtab;
-    struct {
-        Elf32_Word nbucket;
-        Elf32_Word nchain;
-        const Elf32_Word *bucket;
-        const Elf32_Word *chain;
-    } hash;
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int dyld_load(const void *shlib, Elf32_Addr base,
-              Elf32_Addr (*resolve)(void *, const char *), void *resolve_data,
-              struct dyld_info *info, const char **error_out);
-void *dyld_lookup(const char *symbol, struct dyld_info *info);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DYLD_H */

litex/soc/software/include/dyld/link.h

@@ -1,28 +0,0 @@
-#ifndef __LINK_H
-#define __LINK_H
-
-#include <stddef.h>
-#include <elf.h>
-
-#define ElfW(type) Elf32_##type
-
-struct dl_phdr_info {
-  ElfW(Addr) dlpi_addr;
-  const char *dlpi_name;
-  const ElfW(Phdr) *dlpi_phdr;
-  ElfW(Half) dlpi_phnum;
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern int dl_iterate_phdr (int (*__callback) (struct dl_phdr_info *,
-                                               size_t, void *),
-                            void *__data);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LINK_H */

litex/soc/software/include/fdlibm/fdlibm.h

@@ -1,216 +0,0 @@
-
-/* @(#)fdlibm.h 1.5 04/04/22 */
-/*
- * ====================================================
- * Copyright (C) 2004 by Sun Microsystems, Inc. All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this
- * software is freely granted, provided that this notice
- * is preserved.
- * ====================================================
- */
-
-/* Sometimes it's necessary to define __LITTLE_ENDIAN explicitly
-   but these catch some common cases. */
-
-#if defined(i386) || defined(i486) || \
-  defined(intel) || defined(x86) || defined(i86pc) || \
-  defined(__alpha) || defined(__osf__)
-#define __LITTLE_ENDIAN
-#endif
-
-#ifdef __LITTLE_ENDIAN
-#define __HI(x) *(1+(int*)&x)
-#define __LO(x) *(int*)&x
-#define __HIp(x) *(1+(int*)x)
-#define __LOp(x) *(int*)x
-#else
-#define __HI(x) *(int*)&x
-#define __LO(x) *(1+(int*)&x)
-#define __HIp(x) *(int*)x
-#define __LOp(x) *(1+(int*)x)
-#endif
-
-#ifdef __STDC__
-#define __P(p)  p
-#else
-#define __P(p)  ()
-#endif
-
-/*
- * ANSI/POSIX
- */
-
-extern int signgam;
-
-#define MAXFLOAT  ((float)3.40282346638528860e+38)
-
-enum fdversion {fdlibm_ieee = -1, fdlibm_svid, fdlibm_xopen, fdlibm_posix};
-
-#define _LIB_VERSION_TYPE enum fdversion
-#define _LIB_VERSION _fdlib_version
-
-/* if global variable _LIB_VERSION is not desirable, one may
- * change the following to be a constant by:
- *  #define _LIB_VERSION_TYPE const enum version
- * In that case, after one initializes the value _LIB_VERSION (see
- * s_lib_version.c) during compile time, it cannot be modified
- * in the middle of a program
- */
-extern  _LIB_VERSION_TYPE  _LIB_VERSION;
-
-#define _IEEE_  fdlibm_ieee
-#define _SVID_  fdlibm_svid
-#define _XOPEN_ fdlibm_xopen
-#define _POSIX_ fdlibm_posix
-
-struct exception {
-  int type;
-  char *name;
-  double arg1;
-  double arg2;
-  double retval;
-};
-
-#define HUGE    MAXFLOAT
-
-/*
- * set X_TLOSS = pi*2**52, which is possibly defined in <values.h>
- * (one may replace the following line by "#include <values.h>")
- */
-
-#define X_TLOSS   1.41484755040568800000e+16
-
-#define DOMAIN    1
-#define SING    2
-#define OVERFLOW  3
-#define UNDERFLOW 4
-#define TLOSS   5
-#define PLOSS   6
-
-/*
- * ANSI/POSIX
- */
-extern double acos __P((double));
-extern double asin __P((double));
-extern double atan __P((double));
-extern double atan2 __P((double, double));
-extern double cos __P((double));
-extern double sin __P((double));
-extern double tan __P((double));
-
-extern double cosh __P((double));
-extern double sinh __P((double));
-extern double tanh __P((double));
-
-extern double exp __P((double));
-extern double frexp __P((double, int *));
-extern double ldexp __P((double, int));
-extern double log __P((double));
-extern double log10 __P((double));
-extern double modf __P((double, double *));
-
-extern double pow __P((double, double));
-extern double sqrt __P((double));
-
-extern double ceil __P((double));
-extern double fabs __P((double));
-extern double floor __P((double));
-extern double fmod __P((double, double));
-
-extern double erf __P((double));
-extern double erfc __P((double));
-extern double gamma __P((double));
-extern double hypot __P((double, double));
-extern int isnan __P((double));
-extern int finite __P((double));
-extern double j0 __P((double));
-extern double j1 __P((double));
-extern double jn __P((int, double));
-extern double lgamma __P((double));
-extern double y0 __P((double));
-extern double y1 __P((double));
-extern double yn __P((int, double));
-
-extern double acosh __P((double));
-extern double asinh __P((double));
-extern double atanh __P((double));
-extern double cbrt __P((double));
-extern double logb __P((double));
-extern double nextafter __P((double, double));
-extern double remainder __P((double, double));
-#ifdef _SCALB_INT
-extern double scalb __P((double, int));
-#else
-extern double scalb __P((double, double));
-#endif
-
-extern int matherr __P((struct exception *));
-
-/*
- * IEEE Test Vector
- */
-extern double significand __P((double));
-
-/*
- * Functions callable from C, intended to support IEEE arithmetic.
- */
-extern double copysign __P((double, double));
-extern int ilogb __P((double));
-extern double rint __P((double));
-extern double scalbn __P((double, int));
-
-/*
- * BSD math library entry points
- */
-extern double expm1 __P((double));
-extern double log1p __P((double));
-
-/*
- * Reentrant version of gamma & lgamma; passes signgam back by reference
- * as the second argument; user must allocate space for signgam.
- */
-#ifdef _REENTRANT
-extern double gamma_r __P((double, int *));
-extern double lgamma_r __P((double, int *));
-#endif  /* _REENTRANT */
-
-/* ieee style elementary functions */
-extern double __ieee754_sqrt __P((double));
-extern double __ieee754_acos __P((double));
-extern double __ieee754_acosh __P((double));
-extern double __ieee754_log __P((double));
-extern double __ieee754_atanh __P((double));
-extern double __ieee754_asin __P((double));
-extern double __ieee754_atan2 __P((double,double));
-extern double __ieee754_exp __P((double));
-extern double __ieee754_cosh __P((double));
-extern double __ieee754_fmod __P((double,double));
-extern double __ieee754_pow __P((double,double));
-extern double __ieee754_lgamma_r __P((double,int *));
-extern double __ieee754_gamma_r __P((double,int *));
-extern double __ieee754_lgamma __P((double));
-extern double __ieee754_gamma __P((double));
-extern double __ieee754_log10 __P((double));
-extern double __ieee754_sinh __P((double));
-extern double __ieee754_hypot __P((double,double));
-extern double __ieee754_j0 __P((double));
-extern double __ieee754_j1 __P((double));
-extern double __ieee754_y0 __P((double));
-extern double __ieee754_y1 __P((double));
-extern double __ieee754_jn __P((int,double));
-extern double __ieee754_yn __P((int,double));
-extern double __ieee754_remainder __P((double,double));
-extern int    __ieee754_rem_pio2 __P((double,double*));
-#ifdef _SCALB_INT
-extern double __ieee754_scalb __P((double,int));
-#else
-extern double __ieee754_scalb __P((double,double));
-#endif
-
-/* fdlibm kernel function */
-extern double __kernel_standard __P((double,double,int));
-extern double __kernel_sin __P((double,double,int));
-extern double __kernel_cos __P((double,double));
-extern double __kernel_tan __P((double,double,int));
-extern int    __kernel_rem_pio2 __P((double*,double*,int,int,int,const int*));

litex/soc/software/libbase/Makefile

@@ -1,51 +1,29 @@
 include ../include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
-OBJECTS = exception.o \
-	libc.o            \
-	errno.o           \
-	crc16.o           \
-	crc32.o           \
-	console.o         \
-	system.o          \
-	id.o              \
-	uart.o            \
-	time.o            \
-	qsort.o           \
-	strtod.o          \
-	spiflash.o        \
-	strcasecmp.o      \
-	i2c.o             \
-	div64.o           \
-	progress.o        \
-	memtest.o         \
-	sim_debug.o
+OBJECTS =  \
+	crc16.o    \
+	crc32.o    \
+	system.o   \
+	progress.o \
+	memtest.o  \
+	uart.o     \
+	spiflash.o \
+	i2c.o
 
-all: crt0.o libbase.a libbase-nofloat.a
+all: libbase.a
 
-libbase.a: $(OBJECTS) vsnprintf.o
-	$(AR) crs libbase.a $(OBJECTS) vsnprintf.o
-
-libbase-nofloat.a: $(OBJECTS) vsnprintf-nofloat.o
-	$(AR) crs libbase-nofloat.a $(OBJECTS) vsnprintf-nofloat.o
+libbase.a: $(OBJECTS)
+	$(AR) crs libbase.a $(OBJECTS)
 
 # pull in dependency info for *existing* .o files
 -include $(OBJECTS:.o=.d)
 
-vsnprintf-nofloat.o: $(LIBBASE_DIRECTORY)/vsnprintf.c
-	$(call compile,-DNO_FLOAT)
-
 %.o: $(LIBBASE_DIRECTORY)/%.c
 	$(compile)
 
-%.o: $(LIBBASE_DIRECTORY)/%.S
-	$(assemble)
-
-crt0.o: $(CPU_DIRECTORY)/crt0.S
-	$(assemble)
-
 .PHONY: all clean
 
 clean:
-	$(RM) $(OBJECTS) crt0.o vsnprintf.o vsnprintf-nofloat.o
-	$(RM) libbase.a libbase-nofloat.a .*~ *~
+	$(RM) $(OBJECTS)
+	$(RM) libbase.a .*~ *~

litex/soc/software/libbase/console.h

@@ -12,10 +12,10 @@ typedef int (*console_read_nonblock_hook)(void);
 void console_set_write_hook(console_write_hook h);
 void console_set_read_hook(console_read_hook r, console_read_nonblock_hook rn);
 
-char readchar(void);
-int readchar_nonblock(void);
+#define readchar getchar
+#define putsnonl(X) fputs(X, stdout)
 
-void putsnonl(const char *s);
+int readchar_nonblock(void);
 
 #ifdef __cplusplus
 }

litex/soc/software/libbase/crc16.c

@@ -1,4 +1,4 @@
-#include <crc.h>
+#include "crc.h"
 
 #ifndef SMALL_CRC
 static const unsigned int crc16_table[256] = {

litex/soc/software/libbase/crc32.c

@@ -3,7 +3,7 @@
  * For conditions of distribution and use, see copyright notice in zlib.h
  */
 
-#include <crc.h>
+#include "crc.h"
 
 #ifndef SMALL_CRC
 static const unsigned int crc_table[256] = {

litex/soc/software/libbase/div64.c

@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
- *
- * Based on former do_div() implementation from asm-parisc/div64.h:
- *	Copyright (C) 1999 Hewlett-Packard Co
- *	Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
- *
- *
- * Generic C version of 64bit/32bit division and modulo, with
- * 64bit result and 32bit remainder.
- *
- * The fast case for (n>>32 == 0) is handled inline by do_div().
- *
- * Code generated for this function might be very inefficient
- * for some CPUs. __div64_32() can be overridden by linking arch-specific
- * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S.
- */
-
-#include <stdint.h>
-
-#include <div64.h>
-
-uint32_t __div64_32(uint64_t *n, uint32_t base)
-{
-	uint64_t rem = *n;
-	uint64_t b = base;
-	uint64_t res, d = 1;
-	uint32_t high = rem >> 32;
-
-	/* Reduce the thing a bit first */
-	res = 0;
-	if (high >= base) {
-		high /= base;
-		res = (uint64_t) high << 32;
-		rem -= (uint64_t) (high*base) << 32;
-	}
-
-	while ((int64_t)b > 0 && b < rem) {
-		b = b+b;
-		d = d+d;
-	}
-
-	do {
-		if (rem >= b) {
-			rem -= b;
-			res += d;
-		}
-		b >>= 1;
-		d >>= 1;
-	} while (d);
-
-	*n = res;
-	return rem;
-}

litex/soc/software/libbase/errno.c

@@ -1,208 +0,0 @@
-#include <string.h>
-#include <errno.h>
-
-int errno;
-
-/************************************************************************
- * Based on: lib/string/lib_strerror.c
- *
- *   Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************/
-
-struct errno_strmap_s
-{
-  int errnum;
-  char *str;
-};
-
-/* This table maps all error numbers to descriptive strings.
- * The only assumption that the code makes with regard to this
- * this table is that it is order by error number.
- *
- * The size of this table is quite large.  Its size can be
- * reduced by eliminating some of the more obscure error
- * strings.
- */
-
-struct errno_strmap_s g_errnomap[] =
-{
-  { EPERM,               EPERM_STR           },
-  { ENOENT,              ENOENT_STR          },
-  { ESRCH,               ESRCH_STR           },
-  { EINTR,               EINTR_STR           },
-  { EIO,                 EIO_STR             },
-  { ENXIO,               ENXIO_STR           },
-  { E2BIG,               E2BIG_STR           },
-  { ENOEXEC,             ENOEXEC_STR         },
-  { EBADF,               EBADF_STR           },
-  { ECHILD,              ECHILD_STR          },
-  { EAGAIN,              EAGAIN_STR          },
-  { ENOMEM,              ENOMEM_STR          },
-  { EACCES,              EACCES_STR          },
-  { EFAULT,              EFAULT_STR          },
-  { ENOTBLK,             ENOTBLK_STR         },
-  { EBUSY,               EBUSY_STR           },
-  { EEXIST,              EEXIST_STR          },
-  { EXDEV,               EXDEV_STR           },
-  { ENODEV,              ENODEV_STR          },
-  { ENOTDIR,             ENOTDIR_STR         },
-  { EISDIR,              EISDIR_STR          },
-  { EINVAL,              EINVAL_STR          },
-  { ENFILE,              ENFILE_STR          },
-  { EMFILE,              EMFILE_STR          },
-  { ENOTTY,              ENOTTY_STR          },
-  { ETXTBSY,             ETXTBSY_STR         },
-  { EFBIG,               EFBIG_STR           },
-  { ENOSPC,              ENOSPC_STR          },
-  { ESPIPE,              ESPIPE_STR          },
-  { EROFS,               EROFS_STR           },
-  { EMLINK,              EMLINK_STR          },
-  { EPIPE,               EPIPE_STR           },
-  { EDOM,                EDOM_STR            },
-  { ERANGE,              ERANGE_STR          },
-  { EDEADLK,             EDEADLK_STR         },
-  { ENAMETOOLONG,        ENAMETOOLONG_STR    },
-  { ENOLCK,              ENOLCK_STR          },
-  { ENOSYS,              ENOSYS_STR          },
-  { ENOTEMPTY,           ENOTEMPTY_STR       },
-  { ELOOP,               ELOOP_STR           },
-  { ENOMSG,              ENOMSG_STR          },
-  { EIDRM,               EIDRM_STR           },
-  { ECHRNG,              ECHRNG_STR          },
-  { EL2NSYNC,            EL2NSYNC_STR        },
-  { EL3HLT,              EL3HLT_STR          },
-  { EL3RST,              EL3RST_STR          },
-  { ELNRNG,              ELNRNG_STR          },
-  { EUNATCH,             EUNATCH_STR         },
-  { ENOCSI,              ENOCSI_STR          },
-  { EL2HLT,              EL2HLT_STR          },
-  { EBADE,               EBADE_STR           },
-  { EBADR,               EBADR_STR           },
-  { EXFULL,              EXFULL_STR          },
-  { ENOANO,              ENOANO_STR          },
-  { EBADRQC,             EBADRQC_STR         },
-  { EBADSLT,             EBADSLT_STR         },
-  { EBFONT,              EBFONT_STR          },
-  { ENOSTR,              ENOSTR_STR          },
-  { ENODATA,             ENODATA_STR         },
-  { ETIME,               ETIME_STR           },
-  { ENOSR,               ENOSR_STR           },
-  { ENONET,              ENONET_STR          },
-  { ENOPKG,              ENOPKG_STR          },
-  { EREMOTE,             EREMOTE_STR         },
-  { ENOLINK,             ENOLINK_STR         },
-  { EADV,                EADV_STR            },
-  { ESRMNT,              ESRMNT_STR          },
-  { ECOMM,               ECOMM_STR           },
-  { EPROTO,              EPROTO_STR          },
-  { EMULTIHOP,           EMULTIHOP_STR       },
-  { EDOTDOT,             EDOTDOT_STR         },
-  { EBADMSG,             EBADMSG_STR         },
-  { EOVERFLOW,           EOVERFLOW_STR       },
-  { ENOTUNIQ,            ENOTUNIQ_STR        },
-  { EBADFD,              EBADFD_STR          },
-  { EREMCHG,             EREMCHG_STR         },
-  { ELIBACC,             ELIBACC_STR         },
-  { ELIBBAD,             ELIBBAD_STR         },
-  { ELIBSCN,             ELIBSCN_STR         },
-  { ELIBMAX,             ELIBMAX_STR         },
-  { ELIBEXEC,            ELIBEXEC_STR        },
-  { EILSEQ,              EILSEQ_STR          },
-  { ERESTART,            ERESTART_STR        },
-  { ESTRPIPE,            ESTRPIPE_STR        },
-  { EUSERS,              EUSERS_STR          },
-  { ENOTSOCK,            ENOTSOCK_STR        },
-  { EDESTADDRREQ,        EDESTADDRREQ_STR    },
-  { EMSGSIZE,            EMSGSIZE_STR        },
-  { EPROTOTYPE,          EPROTOTYPE_STR      },
-  { ENOPROTOOPT,         ENOPROTOOPT_STR     },
-  { EPROTONOSUPPORT,     EPROTONOSUPPORT_STR },
-  { ESOCKTNOSUPPORT,     ESOCKTNOSUPPORT_STR },
-  { EOPNOTSUPP,          EOPNOTSUPP_STR      },
-  { EPFNOSUPPORT,        EPFNOSUPPORT_STR    },
-  { EAFNOSUPPORT,        EAFNOSUPPORT_STR    },
-  { EADDRINUSE,          EADDRINUSE_STR      },
-  { EADDRNOTAVAIL,       EADDRNOTAVAIL_STR   },
-  { ENETDOWN,            ENETDOWN_STR        },
-  { ENETUNREACH,         ENETUNREACH_STR     },
-  { ENETRESET,           ENETRESET_STR       },
-  { ECONNABORTED,        ECONNABORTED_STR    },
-  { ECONNRESET,          ECONNRESET_STR      },
-  { ENOBUFS,             ENOBUFS_STR         },
-  { EISCONN,             EISCONN_STR         },
-  { ENOTCONN,            ENOTCONN_STR        },
-  { ESHUTDOWN,           ESHUTDOWN_STR       },
-  { ETOOMANYREFS,        ETOOMANYREFS_STR    },
-  { ETIMEDOUT,           ETIMEDOUT_STR       },
-  { ECONNREFUSED,        ECONNREFUSED_STR    },
-  { EHOSTDOWN,           EHOSTDOWN_STR       },
-  { EHOSTUNREACH,        EHOSTUNREACH_STR    },
-  { EALREADY,            EALREADY_STR        },
-  { EINPROGRESS,         EINPROGRESS_STR     },
-  { ESTALE,              ESTALE_STR          },
-  { EUCLEAN,             EUCLEAN_STR         },
-  { ENOTNAM,             ENOTNAM_STR         },
-  { ENAVAIL,             ENAVAIL_STR         },
-  { EISNAM,              EISNAM_STR          },
-  { EREMOTEIO,           EREMOTEIO_STR       },
-  { EDQUOT,              EDQUOT_STR          },
-  { ENOMEDIUM,           ENOMEDIUM_STR       },
-  { EMEDIUMTYPE,         EMEDIUMTYPE_STR     }
-};
-
-#define NERRNO_STRS (sizeof(g_errnomap) / sizeof(struct errno_strmap_s))
-
-char *strerror(int errnum)
-{
-  int ndxlow = 0;
-  int ndxhi  = NERRNO_STRS - 1;
-  int ndxmid;
-
-  do
-    {
-      ndxmid = (ndxlow + ndxhi) >> 1;
-      if (errnum > g_errnomap[ndxmid].errnum)
-        {
-          ndxlow = ndxmid + 1;
-        }
-      else if (errnum < g_errnomap[ndxmid].errnum)
-        {
-          ndxhi = ndxmid - 1;
-        }
-      else
-        {
-          return g_errnomap[ndxmid].str;
-        }
-    }
-  while (ndxlow <= ndxhi);
-  return "Unknown error";
-}

litex/soc/software/libbase/i2c.c

@@ -1,5 +1,6 @@
 // This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
-#include <i2c.h>
+#include "i2c.h"
+
 #include <generated/csr.h>
 
 #ifdef CSR_I2C_BASE

litex/soc/software/libbase/id.c

@@ -1,18 +0,0 @@
-#include <generated/csr.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <id.h>
-
-#define DFII_ADDR_SHIFT CONFIG_CSR_ALIGNMENT/8
-
-void get_ident(char *ident)
-{
-#ifdef CSR_IDENTIFIER_MEM_BASE
-    int i;
-    for(i=0;i<256;i++)
-        ident[i] = MMPTR(CSR_IDENTIFIER_MEM_BASE + DFII_ADDR_SHIFT*i);
-#else
-    ident[0] = 0;
-#endif
-}