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test: change UART baudrate and test SATACONTRemover

This commit is contained in:
Florent Kermarrec 2014-12-19 17:45:02 +01:00
parent 33eed1aa79
commit 880c7e7ecc
3 changed files with 12 additions and 24 deletions
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25
targets/test.py
View File

@ -60,7 +60,7 @@ class UART2WB(Module):
interrupt_map = {} interrupt_map = {}
cpu_type = None cpu_type = None
def __init__(self, platform, clk_freq): def __init__(self, platform, clk_freq):
self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq) self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)
# CSR bridge 0x00000000 (shadow @0x00000000) # CSR bridge 0x00000000 (shadow @0x00000000)
self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
@ -159,7 +159,8 @@ class VeryBasicPHYStim(Module, AutoCSR):
self.cont_remover = SATACONTRemover(phy_description(32)) self.cont_remover = SATACONTRemover(phy_description(32))
self.comb += [ self.comb += [
self.cont_inserter.source.connect(phy.sink), self.cont_inserter.source.connect(phy.sink),
phy.source.connect(self.cont_remover.sink) phy.source.connect(self.cont_remover.sink),
self.cont_remover.source.ack.eq(1)
] ]
self.sync += [ self.sync += [
self.cont_inserter.sink.stb.eq(1), self.cont_inserter.sink.stb.eq(1),
@ -201,20 +202,6 @@ class TestDesign(UART2WB, AutoCSR):
crg = self.sata_phy.crg crg = self.sata_phy.crg
debug = ( debug = (
trx.rxresetdone,
trx.txresetdone,
trx.rxuserrdy,
trx.txuserrdy,
trx.rxelecidle,
trx.rxcominitdet,
trx.rxcomwakedet,
trx.txcomfinish,
trx.txcominit,
trx.txcomwake,
ctrl.ready, ctrl.ready,
ctrl.sink.data, ctrl.sink.data,
ctrl.sink.charisk, ctrl.sink.charisk,
@ -226,12 +213,16 @@ class TestDesign(UART2WB, AutoCSR):
self.sata_phy.sink.stb, self.sata_phy.sink.stb,
self.sata_phy.sink.data, self.sata_phy.sink.data,
self.sata_phy.sink.charisk, self.sata_phy.sink.charisk,
self.stim.cont_remover.source.stb,
self.stim.cont_remover.source.data,
self.stim.cont_remover.source.charisk
) )
self.comb += platform.request("user_led", 2).eq(crg.ready) self.comb += platform.request("user_led", 2).eq(crg.ready)
self.comb += platform.request("user_led", 3).eq(ctrl.ready) self.comb += platform.request("user_led", 3).eq(ctrl.ready)
self.mila = MiLa(depth=512, dat=Cat(*debug)) self.mila = MiLa(depth=2048, dat=Cat(*debug))
self.mila.add_port(Term) self.mila.add_port(Term)
if export_mila: if export_mila:

2
test/config.py
View File

@ -5,5 +5,5 @@ busword = 8
debug_wb = False debug_wb = False
com = 2 com = 2
baud = 115200 baud = 921600
wb = Uart2Wishbone(com, baud, csr_csv_file, busword, debug_wb) wb = Uart2Wishbone(com, baud, csr_csv_file, busword, debug_wb)

9
test/test_mila.py
View File

@ -4,11 +4,8 @@ from miscope.host.drivers import MiLaDriver
mila = MiLaDriver(wb.regs, "mila", use_rle=False) mila = MiLaDriver(wb.regs, "mila", use_rle=False)
wb.open() wb.open()
### ###
trigger0 = mila.trx_rxelecidle0_o*0 trigger0 = mila.cont_remover_source_stb_o*1
mask0 = mila.trx_rxelecidle0_m mask0 = mila.cont_remover_source_stb_m
#trigger0 = mila.ctrl_align_detect_o
#mask0 = mila.ctrl_align_detect_m
trigger0 = 0 trigger0 = 0
mask0 = 0 mask0 = 0
@ -17,7 +14,7 @@ mila.prog_term(port=0, trigger=trigger0, mask=mask0)
mila.prog_sum("term") mila.prog_sum("term")
# Trigger / wait / receive # Trigger / wait / receive
mila.trigger(offset=8, length=512) mila.trigger(offset=32, length=1024)
mila.wait_done() mila.wait_done()
mila.read() mila.read()
mila.export("dump.vcd") mila.export("dump.vcd")