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Merge pull request #1721 from rasmuspeders1/master

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Make litex_json2renode work with default arty target SOC .json file
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Tim 'mithro' Ansell 2023-06-30 10:05:45 -07:00 committed by GitHub
commit 886994aaa4
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1 changed files with 5 additions and 4 deletions
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5
litex/tools/litex_json2renode.py
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@ -214,7 +214,7 @@ def get_cpu_type(csr):
return (kind, variant)
def get_cpu_count(csr):
return csr['constants']['config_cpu_count']
return csr['constants'].get('config_cpu_count', 1)
vexriscv_common_kind = {
'name': 'VexRiscv',
@ -297,7 +297,7 @@ def generate_cpu(csr, time_provider, number_of_cores):
cpu{cpu_id}: CPU.{cpu_string.strip()}
hartId: {cpu_id}
"""
if cpu.get('supports_time_provider', False):
if cpu.get('supports_time_provider', False) and time_provider:
result += f' timeProvider: {time_provider}\n'
return result
@ -889,6 +889,7 @@ showAnalyzer sysbus.uart Antmicro.Renode.Analyzers.LoggingUartAnalyzer
sysbus LoadBinary @{} {}
""".format(args.bios_binary, hex(opensbi_base))
if opensbi_base:
for cpu_id in range(0, number_of_cores):
result += f"cpu{cpu_id} PC {hex(opensbi_base)}\n"