simplify recorder

This commit is contained in:
Florent Kermarrec 2013-03-23 12:26:22 +01:00
parent 99a78b8e33
commit 88748bd74f
2 changed files with 23 additions and 41 deletions

View File

@ -85,26 +85,18 @@ class Sequencer:
# #
# Definition # Definition
# #
def __init__(self,depth): def __init__(self):
self.depth = depth
self.depth_width = bits_for(self.depth)
# Controller interface # Controller interface
self.ctl_rst = Signal() self.rst = Signal()
self.ctl_offset = Signal(self.depth_width) self.arm = Signal()
self.ctl_size = Signal(self.depth_width)
self.ctl_arm = Signal()
self.ctl_done = Signal()
self._ctl_arm_d = Signal()
# Trigger interface # Trigger interface
self.hit = Signal() self.hit = Signal()
# Recorder interface # Recorder interface
self.rec_offset = Signal(self.depth_width) self.start = Signal()
self.rec_size = Signal(self.depth_width) self.done = Signal()
self.rec_start = Signal()
self.rec_done = Signal()
# Others # Others
self.enable = Signal() self.enable = Signal()
@ -116,28 +108,23 @@ class Sequencer:
# Idle # Idle
fsm.act(fsm.IDLE, fsm.act(fsm.IDLE,
If(self.ctl_arm, If(self.arm,
fsm.next_state(fsm.ACTIVE), fsm.next_state(fsm.ACTIVE),
) )
) )
# Active # Active
fsm.act(fsm.ACTIVE, fsm.act(fsm.ACTIVE,
If(self.rec_done | self.ctl_rst, If(self.done | self.rst,
fsm.next_state(fsm.IDLE), fsm.next_state(fsm.IDLE),
), ),
self.enable.eq(1) self.enable.eq(1)
) )
# Start
hit_rising = RisingEdge(self.hit) hit_rising = RisingEdge(self.hit)
comb =[self.start.eq(self.enable & hit_rising.o)]
# connexion
comb = [
self.rec_offset.eq(self.ctl_offset),
self.rec_size.eq(self.ctl_size),
self.rec_start.eq(self.enable & hit_rising.o),
self.ctl_done.eq(~self.enable),
]
return Fragment(comb) + fsm.get_fragment() + hit_rising.get_fragment() return Fragment(comb) + fsm.get_fragment() + hit_rising.get_fragment()
@ -159,7 +146,7 @@ class Recorder:
self.depth_width = bits_for(self.depth-1) self.depth_width = bits_for(self.depth-1)
self.storage = Storage(self.width, self.depth) self.storage = Storage(self.width, self.depth)
self.sequencer = Sequencer(self.depth) self.sequencer = Sequencer()
# csr interface # csr interface
self._rst = RegisterField("rst", reset=1) self._rst = RegisterField("rst", reset=1)
@ -198,14 +185,14 @@ class Recorder:
# Bank <--> Storage / Sequencer # Bank <--> Storage / Sequencer
comb = [ comb = [
self.sequencer.ctl_rst.eq(self._rst.field.r), self.sequencer.rst.eq(self._rst.field.r),
self.storage.rst.eq(self._rst.field.r), self.storage.rst.eq(self._rst.field.r),
self.sequencer.ctl_offset.eq(self._offset.field.r), self.sequencer.arm.eq(self._arm.field.r),
self.sequencer.ctl_size.eq(self._size.field.r), self.storage.offset.eq(self._offset.field.r),
self.sequencer.ctl_arm.eq(self._arm.field.r), self.storage.size.eq(self._size.field.r),
self._done.field.w.eq(self.sequencer.ctl_done), self._done.field.w.eq(~self.sequencer.enable),
self.storage.pull_stb.eq(_pull_stb_rising.o), self.storage.pull_stb.eq(_pull_stb_rising.o),
self._pull_dat.field.w.eq(self.storage.pull_dat) self._pull_dat.field.w.eq(self.storage.pull_dat)
@ -213,11 +200,8 @@ class Recorder:
# Storage <--> Sequencer <--> Trigger # Storage <--> Sequencer <--> Trigger
comb += [ comb += [
self.storage.offset.eq(self.sequencer.rec_offset), self.storage.start.eq(self.sequencer.start),
self.storage.size.eq(self.sequencer.rec_size), self.sequencer.done.eq(self.storage.done),
self.storage.start.eq(self.sequencer.rec_start),
self.sequencer.rec_done.eq(self.storage.done),
self.sequencer.hit.eq(self.hit), self.sequencer.hit.eq(self.hit),
self.storage.push_stb.eq(self.sequencer.enable), self.storage.push_stb.eq(self.sequencer.enable),

View File

@ -198,7 +198,6 @@ class Sum:
self.interface = None self.interface = None
self.i = Signal(self.width) self.i = Signal(self.width)
self._o = Signal()
self.o = Signal() self.o = Signal()
self.reg_p = RegParams("sum_reg", 0, 8, 4) self.reg_p = RegParams("sum_reg", 0, 8, 4)
@ -223,13 +222,12 @@ class Sum:
def get_fragment(self): def get_fragment(self):
comb = [ comb = [
self._lut_port.adr.eq(self.i), self._lut_port.adr.eq(self.i),
self._o.eq(self._lut_port.dat_r),
self._prog_port.adr.eq(self.prog_adr), self._prog_port.adr.eq(self.prog_adr),
self._prog_port.we.eq(self.prog_stb), self._prog_port.we.eq(self.prog_stb),
self._prog_port.dat_w.eq(self.prog_dat), self._prog_port.dat_w.eq(self.prog_dat),
self.o.eq(self._o) self.o.eq(self._lut_port.dat_r),
] ]
comb += self.get_registers_comb() comb += self.get_registers_comb()
return Fragment(comb, specials={self._mem}) return Fragment(comb, specials={self._mem})