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update LiteScope

This commit is contained in:
Florent Kermarrec 2015-01-25 16:21:56 +01:00
parent d97ec9235b
commit 8887bea721
3 changed files with 15 additions and 13 deletions
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2
README
View File

@ -12,7 +12,7 @@
--------- ---------
LiteSATA provides a small footprint and configurable SATA gen1/2/3 core. LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
FPGA IP cores by providing simple, elegant and efficient implementations of FPGA IP cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

10
targets/bist.py
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@ -13,7 +13,7 @@ from misoclib import identifier
from litescope.common import * from litescope.common import *
from litescope.bridge.uart2wb import LiteScopeUART2WB from litescope.bridge.uart2wb import LiteScopeUART2WB
from litescope.frontend.la import LiteScopeLA from litescope.frontend.la import LiteScopeLA
from litescope.core.trigger import LiteScopeTerm from litescope.core.port import LiteScopeTerm
from litesata.common import * from litesata.common import *
from litesata.phy import LiteSATAPHY from litesata.phy import LiteSATAPHY
@ -164,7 +164,7 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
self.sata_core_command_rx_fsm_state = Signal(4) self.sata_core_command_rx_fsm_state = Signal(4)
self.sata_core_command_tx_fsm_state = Signal(4) self.sata_core_command_tx_fsm_state = Signal(4)
self.debug = ( debug = (
self.sata_phy.ctrl.ready, self.sata_phy.ctrl.ready,
self.sata_phy.source.stb, self.sata_phy.source.stb,
@ -201,8 +201,8 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
self.sata_core_command_tx_fsm_state, self.sata_core_command_tx_fsm_state,
) )
self.submodules.la = LiteScopeLA(2048, self.debug) self.submodules.la = LiteScopeLA(debug, 2048)
self.la.add_port(LiteScopeTerm) self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
atexit.register(self.exit, platform) atexit.register(self.exit, platform)
def do_finalize(self): def do_finalize(self):
@ -218,6 +218,6 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
def exit(self, platform): def exit(self, platform):
if platform.vns is not None: if platform.vns is not None:
self.la.export(self.debug, platform.vns, "./test/la.csv") self.la.export(platform.vns, "../test/la.csv")
default_subtarget = BISTSoC default_subtarget = BISTSoC

16
test/test_la.py
View File

@ -44,19 +44,21 @@ conditions["rd_resp"] = {
"sata_command_rx_source_payload_read" : 1, "sata_command_rx_source_payload_read" : 1,
} }
la.prog_term(port=0, cond=conditions[trig]) la.configure_term(port=0, cond=conditions[trig])
la.prog_sum("term") la.configure_sum("term")
# Trigger / wait / receive # Run Logic Analyzer
la.trigger(offset=64, length=1024) la.run(offset=64, length=1024)
#identify.run(blocking=False) #identify.run(blocking=False)
generator.run(0, 2, 1, 0, blocking=False) generator.run(0, 2, 1, 0, blocking=False)
#checker.run(0, 2, 1, 0, blocking=False) #checker.run(0, 2, 1, 0, blocking=False)
la.wait_done()
la.read() while not la.done():
la.export("dump.vcd") pass
la.upload()
la.save("dump.vcd")
### ###
wb.close() wb.close()