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build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build). 

Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
This commit is contained in:
Florent Kermarrec 2018-11-27 17:42:39 +01:00
parent ec46beeb47
commit 8887fc24c4
1 changed files with 7 additions and 4 deletions
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9
litex/build/xilinx/vivado.py
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@ -106,9 +106,11 @@ class XilinxVivadoToolchain:
self.clocks = dict() self.clocks = dict()
self.false_paths = set() self.false_paths = set()
def _build_batch(self, platform, sources, edifs, ips, build_name, synth_mode="vivado"): def _build_batch(self, platform, sources, edifs, ips, build_name, synth_mode, enable_xpm):
assert synth_mode in ["vivado", "yosys"]
tcl = [] tcl = []
tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device)) tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device))
if enable_xpm:
tcl.append("set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]") tcl.append("set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]")
if synth_mode == "vivado": if synth_mode == "vivado":
# "-include_dirs {}" crashes Vivado 2016.4 # "-include_dirs {}" crashes Vivado 2016.4
@ -214,7 +216,8 @@ class XilinxVivadoToolchain:
) )
def build(self, platform, fragment, build_dir="build", build_name="top", def build(self, platform, fragment, build_dir="build", build_name="top",
toolchain_path="/opt/Xilinx/Vivado", source=True, run=True, synth_mode="vivado", **kwargs): toolchain_path="/opt/Xilinx/Vivado", source=True, run=True,
synth_mode="vivado", enable_xpm=False, **kwargs):
if toolchain_path is None: if toolchain_path is None:
toolchain_path = "/opt/Xilinx/Vivado" toolchain_path = "/opt/Xilinx/Vivado"
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
@ -233,7 +236,7 @@ class XilinxVivadoToolchain:
sources = platform.sources | {(v_file, "verilog", "work")} sources = platform.sources | {(v_file, "verilog", "work")}
edifs = platform.edifs edifs = platform.edifs
ips = platform.ips ips = platform.ips
self._build_batch(platform, sources, edifs, ips, build_name, synth_mode=synth_mode) self._build_batch(platform, sources, edifs, ips, build_name, synth_mode, enable_xpm)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc)) tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run: if run:
if synth_mode == "yosys": if synth_mode == "yosys":