targets: sync with litex-boards

litex/boards/targets/de0nano.py

@@ -6,8 +6,9 @@
 import argparse
 
 from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.boards.platforms import de0nano
+from litex_boards.platforms import de0nano
 
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
@@ -21,41 +22,50 @@ class _CRG(Module):
     def __init__(self, platform):
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain()
-        self.clock_domains.cd_por    = ClockDomain(reset_less=True)
 
         # # #
 
-        # Power on reset
+        # Clk / Rst
-        rst_n = Signal()
-        self.sync.por += rst_n.eq(1)
-        self.comb += [
-            self.cd_por.clk.eq(self.cd_sys.clk),
-            self.cd_sys.rst.eq(~rst_n),
-            self.cd_sys_ps.rst.eq(~rst_n)
-        ]
-
-        # Sys Clk / SDRAM Clk
         clk50 = platform.request("clk50")
-        self.comb += self.cd_sys.clk.eq(clk50)
+        platform.add_period_constraint(clk50, 1e9/50e6)
+
+        # PLL
+        pll_locked  = Signal()
+        pll_clk_out = Signal(6)
         self.specials += \
             Instance("ALTPLL",
                 p_BANDWIDTH_TYPE         = "AUTO",
                 p_CLK0_DIVIDE_BY         = 1,
                 p_CLK0_DUTY_CYCLE        = 50,
                 p_CLK0_MULTIPLY_BY       = 1,
-                p_CLK0_PHASE_SHIFT       = "-3000",
+                p_CLK0_PHASE_SHIFT       = "0",
+                p_CLK1_DIVIDE_BY         = 1,
+                p_CLK1_DUTY_CYCLE        = 50,
+                p_CLK1_MULTIPLY_BY       = 1,
+                p_CLK1_PHASE_SHIFT       = "-10000",
                 p_COMPENSATE_CLOCK       = "CLK0",
                 p_INCLK0_INPUT_FREQUENCY = 20000,
-                p_OPERATION_MODE         = "ZERO_DELAY_BUFFER",
+                p_OPERATION_MODE         = "NORMAL",
                 i_INCLK                  = clk50,
-                o_CLK                    = self.cd_sys_ps.clk,
+                o_CLK                    = pll_clk_out,
-                i_ARESET                 = ~rst_n,
+                i_ARESET                 = 0,
                 i_CLKENA                 = 0x3f,
                 i_EXTCLKENA              = 0xf,
                 i_FBIN                   = 1,
                 i_PFDENA                 = 1,
                 i_PLLENA                 = 1,
+                o_LOCKED                 = pll_locked,
             )
+        self.comb += [
+            self.cd_sys.clk.eq(pll_clk_out[0]),
+            self.cd_sys_ps.clk.eq(pll_clk_out[1]),
+        ]
+        self.specials += [
+            AsyncResetSynchronizer(self.cd_sys,    ~pll_locked),
+            AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
+        ]
+
+        # SDRAM clock
         self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
 
 # BaseSoC ------------------------------------------------------------------------------------------

litex/boards/targets/versa_ecp5.py

@@ -37,19 +37,19 @@ class _CRG(Module):
 
         self.stop = Signal()
 
-        # clk / rst
+        # Clk / Rst
         clk100 = platform.request("clk100")
         rst_n  = platform.request("rst_n")
         platform.add_period_constraint(clk100, 1e9/100e6)
 
-        # power on reset
+        # Power on reset
         por_count = Signal(16, reset=2**16-1)
         por_done  = Signal()
         self.comb += self.cd_por.clk.eq(ClockSignal())
         self.comb += por_done.eq(por_count == 0)
         self.sync.por += If(~por_done, por_count.eq(por_count - 1))
 
-        # pll
+        # PLL
         self.submodules.pll = pll = ECP5PLL()
         pll.register_clkin(clk100, 100e6)
         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)