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build/xilinx/ise.py: write .v file for post synthesis sim

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Michael Betz 2019-04-23 09:22:48 +02:00 committed by Florent Kermarrec
parent 7396ebbb38
commit 88b882c7e0
1 changed files with 5 additions and 0 deletions
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5
litex/build/xilinx/ise.py
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@ -108,6 +108,11 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
ext = "ngc" ext = "ngc"
build_script_contents += """ build_script_contents += """
xst -ifn {build_name}.xst{fail_stmt} xst -ifn {build_name}.xst{fail_stmt}
"""
# This generates a .v file for post synthesis simulation
build_script_contents += """
netgen -ofmt verilog -w -sim {build_name}.{ext} {build_name}_synth.v
""" """
build_script_contents += """ build_script_contents += """