dvisampler/clocking: insert DCM_CLKGEN before PLL
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f833bc9aa9
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8914969760
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@ -18,6 +18,19 @@ class Clocking(Module, AutoCSR):
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###
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###
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clk_dejitter = Signal()
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dcm_locked = Signal()
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self.specials += Instance("DCM_CLKGEN",
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Instance.Parameter("CLKIN_PERIOD", 26.7),
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Instance.Parameter("CLKFX_DIVIDE", 2),
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Instance.Parameter("CLKFX_MULTIPLY", 2),
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Instance.Parameter("CLKFX_MD_MAX", 1.0),
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Instance.Input("CLKIN", pads.clk),
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Instance.Input("RST", self._r_pll_reset.storage),
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Instance.Output("CLKFX", clk_dejitter),
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Instance.Output("LOCKED", dcm_locked)
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)
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clkfbout = Signal()
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clkfbout = Signal()
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pll_locked = Signal()
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pll_locked = Signal()
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pll_clk0 = Signal()
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pll_clk0 = Signal()
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@ -41,8 +54,8 @@ class Clocking(Module, AutoCSR):
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Instance.Output("CLKOUT3", pll_clk3),
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Instance.Output("CLKOUT3", pll_clk3),
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Instance.Output("LOCKED", pll_locked),
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Instance.Output("LOCKED", pll_locked),
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Instance.Input("CLKFBIN", clkfbout),
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Instance.Input("CLKFBIN", clkfbout),
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Instance.Input("CLKIN", pads.clk),
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Instance.Input("CLKIN", clk_dejitter),
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Instance.Input("RST", self._r_pll_reset.storage)
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Instance.Input("RST", ~dcm_locked)
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)
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)
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locked_async = Signal()
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locked_async = Signal()
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