Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

dvisampler/clocking: insert DCM_CLKGEN before PLL

This commit is contained in:
Sebastien Bourdeauducq 2013-04-14 16:53:19 +02:00
parent f833bc9aa9
commit 8914969760
1 changed files with 15 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
milkymist/dvisampler/clocking.py
View File

@ -18,6 +18,19 @@ class Clocking(Module, AutoCSR):
###
clk_dejitter = Signal()
dcm_locked = Signal()
self.specials += Instance("DCM_CLKGEN",
Instance.Parameter("CLKIN_PERIOD", 26.7),
Instance.Parameter("CLKFX_DIVIDE", 2),
Instance.Parameter("CLKFX_MULTIPLY", 2),
Instance.Parameter("CLKFX_MD_MAX", 1.0),
Instance.Input("CLKIN", pads.clk),
Instance.Input("RST", self._r_pll_reset.storage),
Instance.Output("CLKFX", clk_dejitter),
Instance.Output("LOCKED", dcm_locked)
)
clkfbout = Signal()
pll_locked = Signal()
pll_clk0 = Signal()
@ -41,8 +54,8 @@ class Clocking(Module, AutoCSR):
Instance.Output("CLKOUT3", pll_clk3),
Instance.Output("LOCKED", pll_locked),
Instance.Input("CLKFBIN", clkfbout),
Instance.Input("CLKIN", pads.clk),
Instance.Input("RST", self._r_pll_reset.storage)
Instance.Input("CLKIN", clk_dejitter),
Instance.Input("RST", ~dcm_locked)
)
locked_async = Signal()