boards: Xilinx ac701 dev board support
This commit is contained in:
Vamsi K Vytla
Florent Kermarrec
parent
88b882c7e0
commit
89a590263f
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
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from litex.build.xilinx.ise import XilinxISEToolchain
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_io = [
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("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
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("clk200", 0,
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Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
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),
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("clk156", 0,
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Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
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),
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("serial", 0,
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Subsignal("cts", Pins("V19")),
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Subsignal("rts", Pins("W19")),
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Subsignal("tx", Pins("U19")),
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Subsignal("rx", Pins("T19")),
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IOStandard("LVCMOS18")),
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("eth_clocks", 0,
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Subsignal("tx", Pins("U22")),
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Subsignal("rx", Pins("U21")),
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IOStandard("LVCMOS18")
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),
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("eth", 0,
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Subsignal("rx_ctl", Pins("U14")),
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Subsignal("rx_data", Pins("U17 V17 V16 V14")),
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Subsignal("tx_ctl", Pins("T15")),
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Subsignal("tx_data", Pins("U16 U15 T18 T17")),
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Subsignal("rst_n", Pins("V18")),
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Subsignal("mdc", Pins("W18")),
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Subsignal("mdio", Pins("T14")),
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IOStandard("LVCMOS18"), Misc("SLEW=FAST"), Drive(16)
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"M4 J3 J1 L4 K5 M7 K1 M6",
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"H1 K3 N7 L5 L7 N6 L3 K2"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("N1 M1 H2"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("P1"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("T4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("R1"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("AC6 AC4 AA3 U7 G1 F3 G5 H9"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7",
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"AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4",
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"AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1",
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"Y3 W3 W6 V6 W4 W5 W1 V1",
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"G2 D1 E1 E2 F2 A2 A3 C2",
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"C3 D3 A4 B4 C4 D4 D5 E5",
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"F4 G4 K6 K7 K8 L8 J5 J6",
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"G6 H6 F7 F8 G8 H8 D6 E6"),
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IOStandard("SSTL15")),
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Subsignal("dqs_p", Pins("V8 AD5 AD1 V3 C1 B5 J4 H7"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("W8 AE5 AE1 V2 B1 A5 H4 G7"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("M2"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("L2"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("P4"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("R2"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15"))
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),
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("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
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("gtp_refclk", 0,
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Subsignal("p", Pins("AA13")),
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Subsignal("n", Pins("AB13"))
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),
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("sfp", 0,
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Subsignal("txp", Pins("AC10")),
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Subsignal("txn", Pins("AD10")),
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Subsignal("rxp", Pins("AC12")),
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Subsignal("rxn", Pins("AD12")),
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),
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("sfp_mgt_clk_sel0", 0, Pins("B26"), IOStandard("LVCMOS25")),
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("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
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("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
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("XADC", 0,
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Subsignal("GPIO0", Pins("H17")),
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Subsignal("GPIO1", Pins("E22")),
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Subsignal("GPIO2", Pins("K18")),
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Subsignal("GPIO3", Pins("L19")),
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Subsignal("VAUX0_N", Pins("J16")),
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Subsignal("VAUX0_P", Pins("K15")),
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Subsignal("VAUX8_N", Pins("J15")),
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Subsignal("VAUX8_P", Pins("J14")),
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IOStandard("LVCMOS25")),
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]
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_connectors = [
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('HPC',
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{'CLK0_M2C_N': 'C19',
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'CLK0_M2C_P': 'D19',
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'CLK1_M2C_N': 'H22',
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'CLK1_M2C_P': 'H21',
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'LA00_CC_N': 'C18',
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'LA00_CC_P': 'D18',
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'LA01_CC_N': 'E18',
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'LA01_CC_P': 'E17',
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'LA02_N': 'H15',
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'LA02_P': 'H14',
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'LA03_N': 'F17',
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'LA03_P': 'G17',
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'LA04_N': 'F19',
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'LA04_P': 'F18',
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'LA05_N': 'F15',
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'LA05_P': 'G15',
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'LA06_N': 'F20',
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'LA06_P': 'G19',
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'LA07_N': 'G16',
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'LA07_P': 'H16',
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'LA08_N': 'B17',
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'LA08_P': 'C17',
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'LA09_N': 'D16',
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'LA09_P': 'E16',
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'LA10_N': 'A18',
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'LA10_P': 'A17',
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'LA11_N': 'A19',
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'LA11_P': 'B19',
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'LA12_N': 'D20',
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'LA12_P': 'E20',
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'LA13_N': 'A20',
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'LA13_P': 'B20',
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'LA14_N': 'B21',
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'LA14_P': 'C21',
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'LA15_N': 'A22',
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'LA15_P': 'B22',
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'LA16_N': 'D21',
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'LA16_P': 'E21',
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'LA17_CC_N': 'J21',
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'LA17_CC_P': 'K21',
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'LA18_CC_N': 'G21',
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'LA18_CC_P': 'G20',
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'LA19_N': 'L14',
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'LA19_P': 'M14',
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'LA20_N': 'M17',
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'LA20_P': 'M16',
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'LA21_N': 'H19',
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'LA21_P': 'J19',
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'LA22_N': 'L18',
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'LA22_P': 'L17',
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'LA23_N': 'J20',
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'LA23_P': 'K20',
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'LA24_N': 'H18',
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'LA24_P': 'J18',
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'LA25_N': 'F22',
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'LA25_P': 'G22',
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'LA26_N': 'H24',
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'LA26_P': 'J24',
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'LA27_N': 'E23',
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'LA27_P': 'F23',
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'LA28_N': 'K23',
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'LA28_P': 'K22',
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'LA29_N': 'F24',
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'LA29_P': 'G24',
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'LA30_N': 'D25',
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'LA30_P': 'E25',
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'LA31_N': 'D26',
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'LA31_P': 'E26',
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'LA32_N': 'G26',
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'LA32_P': 'H26',
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'LA33_N': 'F25',
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'LA33_P': 'G25',
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'PRSNT_M2C_L': 'N16',
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'PWR_GOOD_FLASH_RST_B': 'P15'})
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk156"
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default_clk_period = 6.4
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def __init__(self, toolchain="vivado", programmer="vivado"):
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XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors,
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toolchain=toolchain)
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self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.programmer = programmer
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def create_programmer(self):
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if self.programmer == "xc3sprog":
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return XC3SProg("jtaghs1_fast")
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elif self.programmer == "vivado":
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return VivadoProgrammer()
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elif self.programmer == "impact":
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return iMPACT()
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else:
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raise ValueError("{} programmer is not supported".format(programmer))
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").tx, 8.0)
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except ConstraintError:
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pass
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@ -0,0 +1,199 @@
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#!/usr/bin/env python3
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import argparse
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from migen import ClockDomain, Signal, Instance, Module
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from litex.boards.platforms import ac701
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from litex.soc.cores.clock import S7MMCM, S7IDELAYCTRL
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from litex.soc.integration.soc_sdram import (SoCSDRAM, soc_sdram_args,
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soc_sdram_argdict)
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from litex.soc.integration.builder import (builder_args, Builder,
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builder_argdict)
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# from litex.soc.integration.soc_core import mem_decoder
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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from liteeth.phy.a7_1000basex import A7_1000BASEX
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from liteeth.core import LiteEthUDPIPCore
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from liteeth.frontend.etherbone import LiteEthEtherbone
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_clk1x = ClockDomain()
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self.clock_domains.cd_clk2x = ClockDomain()
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self.clk125 = Signal()
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clk125_ds = platform.request("gtp_refclk")
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=clk125_ds.p, i_IB=clk125_ds.n,
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o_O=self.clk125)
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += platform.request("sfp_mgt_clk_sel0", 0).eq(0)
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self.comb += platform.request("sfp_mgt_clk_sel1", 0).eq(0)
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self.comb += platform.request("sfp_tx_disable_n", 0).eq(0)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(self.clk125, 125e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90.0)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_clk1x, 100e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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class BaseSoC(SoCSDRAM):
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csr_map = {
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"ddrphy": 16,
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}
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, clk_freq=125e6, **kwargs):
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platform = ac701.Platform(programmer='xc3sprog')
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sys_clk_freq = int(clk_freq)
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_sram_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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class Debug(Module, AutoCSR):
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def __init__(self, lock, tx_init_done, test):
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self.foo_counter = CSRStatus(26)
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self.lock = CSRStatus(1)
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self.tx_init_done = CSRStatus(1)
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self.test = CSRStatus(1)
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counter = Signal(26)
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self.sync.eth_tx += [counter.eq(counter + 1),
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self.foo_counter.status.eq(counter)]
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self.comb += [
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self.tx_init_done.status.eq(tx_init_done),
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self.lock.status.eq(lock),
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self.test.status.eq(test)
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]
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class EthernetSoC(BaseSoC):
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csr_map = {
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"ethphy": 18,
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"xadc": 19,
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"Debug": 20,
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# "ethmac": 21
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}
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csr_map.update(BaseSoC.csr_map)
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interrupt_map = {
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# "ethmac": 3,
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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mem_map = {
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# "xadc": 0x30000000,
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# "ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def setup_sfp_phy(self):
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self.create_qpll()
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self.submodules.ethphy = A7_1000BASEX(self.ethphy_qpll_channel,
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self.platform.request("sfp", 0),
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self.clk_freq)
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self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
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self.platform.add_period_constraint(self.ethphy.txoutclk, 16.)
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self.platform.add_period_constraint(self.ethphy.rxoutclk, 16.)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.txoutclk, self.ethphy.rxoutclk)
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def setup_rgmii_phy(self):
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self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
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self.platform.request("eth"))
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# self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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# self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.crg.cd_sys.clk.attr.add("keep")
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self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
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self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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def __init__(self, use_sfp=True, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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if use_sfp:
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self.setup_sfp_phy()
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else:
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self.setup_rgmii_phy()
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self.crg.cd_sys.clk.attr.add("keep")
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mac_address = 0x10e2d5000000
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ip_address = 0xc0a80132
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self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address,
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ip_address, self.clk_freq)
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# self.submodules.Debug = Debug(self.ethphy_qpll_channel.lock,
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# self.ethphy.tx_init.done,
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# self.ethphy.tx_init.tx_reset)
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def create_qpll(self):
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qpll_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(self.crg.clk125, qpll_settings)
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self.submodules += qpll
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self.ethphy_qpll_channel = qpll.channels[0]
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|
||||
|
||||
class EtherboneSoC(EthernetSoC):
|
||||
def __init__(self, **kwargs):
|
||||
EthernetSoC.__init__(self, **kwargs)
|
||||
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234,
|
||||
mode="master")
|
||||
self.add_wb_master(self.etherbone.wishbone.bus)
|
||||
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX SoC on AC701")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
parser.add_argument("--with-ethernet", action="store_true",
|
||||
help="enable Ethernet support")
|
||||
args = parser.parse_args()
|
||||
cls = EtherboneSoC if args.with_ethernet else BaseSoC
|
||||
soc = cls(**soc_sdram_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue