litex_sim: Switch to new LiteXArgumentParser and let it handle verilator build args.
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@ -16,7 +16,6 @@ from migen import *
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from litex.build.generic_platform import *
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from litex.build.sim import SimPlatform
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from litex.build.sim.config import SimConfig
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from litex.build.sim.verilator import verilator_build_args, verilator_build_argdict
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from litex.soc.integration.common import *
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from litex.soc.integration.soc_core import *
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@ -363,9 +362,6 @@ def generate_gtkw_savefile(builder, vns, trace_fst):
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dfi_group("dfi commands", ["rddata"])
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def sim_args(parser):
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builder_args(parser)
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soc_core_args(parser)
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verilator_build_args(parser)
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parser.add_argument("--rom-init", default=None, help="ROM init file (.bin or .json).")
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parser.add_argument("--ram-init", default=None, help="RAM init file (.bin or .json).")
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parser.add_argument("--main-ram-init-base", default="0x40000000", help="(SD)RAM base assumed in init file.")
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@ -391,14 +387,13 @@ def sim_args(parser):
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parser.add_argument("--non-interactive", action="store_true", help="Run simulation without user input.")
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC Simulation utility")
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(description="LiteX SoC Simulation utility")
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parser.set_platform(SimPlatform)
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sim_args(parser)
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args = parser.parse_args()
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soc_kwargs = soc_core_argdict(args)
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builder_kwargs = builder_argdict(args)
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verilator_build_kwargs = verilator_build_argdict(args)
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sys_clk_freq = int(1e6)
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sim_config = SimConfig()
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@ -493,12 +488,14 @@ def main():
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if args.trace:
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generate_gtkw_savefile(builder, vns, args.trace_fst)
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builder = Builder(soc, **builder_kwargs)
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builder = Builder(soc, **parser.builder_argdict)
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print(parser.builder_argdict)
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builder.build(
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sim_config = sim_config,
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interactive = not args.non_interactive,
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pre_run_callback = pre_run_callback,
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**verilator_build_kwargs,
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**parser.toolchain_argdict,
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)
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if __name__ == "__main__":
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