soc/interconnect/stream: reintroduce PipelinedActor/Buffer
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@ -200,6 +200,56 @@ class CombinatorialActor(BinaryActor):
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class PipelinedActor(BinaryActor):
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def __init__(self, latency):
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self.pipe_ce = Signal()
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BinaryActor.__init__(self, latency)
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def build_binary_control(self, sink, source, latency):
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busy = 0
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valid = sink.stb
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for i in range(latency):
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valid_n = Signal()
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self.sync += If(self.pipe_ce, valid_n.eq(valid))
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valid = valid_n
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busy = busy | valid
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self.comb += [
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self.pipe_ce.eq(source.ack | ~valid),
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sink.ack.eq(self.pipe_ce),
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source.stb.eq(valid),
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self.busy.eq(busy)
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]
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if sink.description.packetized:
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sop = sink.stb & sink.sop
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eop = sink.stb & sink.eop
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for i in range(latency):
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sop_n = Signal()
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eop_n = Signal()
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self.sync += \
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If(self.pipe_ce,
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sop_n.eq(sop),
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eop_n.eq(eop)
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)
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sop = sop_n
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eop = eop_n
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self.comb += [
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source.eop.eq(eop),
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source.sop.eq(sop)
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]
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class Buffer(PipelinedActor):
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def __init__(self, layout):
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self.d = Sink(layout)
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self.q = Source(layout)
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PipelinedActor.__init__(self, 1)
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self.sync += \
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If(self.pipe_ce,
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self.q.payload.eq(self.d.payload)
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)
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class Unpack(Module):
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class Unpack(Module):
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def __init__(self, n, layout_to, reverse=False):
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def __init__(self, n, layout_to, reverse=False):
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self.source = source = Source(layout_to)
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self.source = source = Source(layout_to)
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