Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

build/generic_platform: use list for sources instead of set

Browse source 
Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
This commit is contained in:
Florent Kermarrec 2018-07-20 10:01:33 +02:00
parent df7e5dbcf6
commit 8a311bf4a6
6 changed files with 7 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/build/altera/quartus.py
View file

@ -127,7 +127,7 @@ class AlteraQuartusToolchain:
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")} sources = platform.sources + [(v_file, "verilog", "work")]
_build_files(platform.device, _build_files(platform.device,
sources, sources,
platform.verilog_include_paths, platform.verilog_include_paths,

4
litex/build/generic_platform.py
View file

@ -261,7 +261,7 @@ class GenericPlatform:
if name is None: if name is None:
name = self.__module__.split(".")[-1] name = self.__module__.split(".")[-1]
self.name = name self.name = name
self.sources = set() self.sources = []
self.verilog_include_paths = set() self.verilog_include_paths = set()
self.finalized = False self.finalized = False
@ -323,7 +323,7 @@ class GenericPlatform:
if library is None: if library is None:
library = "work" library = "work"
self.sources.add((os.path.abspath(filename), language, library)) self.sources.append((os.path.abspath(filename), language, library))
def add_sources(self, path, *filenames, language=None, library=None): def add_sources(self, path, *filenames, language=None, library=None):
for f in filenames: for f in filenames:

2
litex/build/lattice/diamond.py
View file

@ -110,7 +110,7 @@ class LatticeDiamondToolchain:
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")} sources = platform.sources + [(v_file, "verilog", "work")]
_build_files(platform.device, sources, platform.verilog_include_paths, build_name) _build_files(platform.device, sources, platform.verilog_include_paths, build_name)
tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc)) tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))

2
litex/build/lattice/icestorm.py
View file

@ -173,7 +173,7 @@ class LatticeIceStormToolchain:
return series_size_str[2:] return series_size_str[2:]
def gen_read_files(self, platform, main): def gen_read_files(self, platform, main):
sources = platform.sources | {(main, "verilog", "work")} sources = platform.sources + [(main, "verilog", "work")]
incflags = "" incflags = ""
read_files = list() read_files = list()
for path in platform.verilog_include_paths: for path in platform.verilog_include_paths:

2
litex/build/xilinx/ise.py
View file

@ -181,7 +181,7 @@ class XilinxISEToolchain:
named_sc, named_pc = platform.resolve_signals(vns) named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")} sources = platform.sources + [(v_file, "verilog", "work")]
if mode in ("xst", "cpld"): if mode in ("xst", "cpld"):
_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt) _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
isemode = mode isemode = mode

2
litex/build/xilinx/vivado.py
View file

@ -223,7 +223,7 @@ class XilinxVivadoToolchain:
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")} sources = platform.sources + [(v_file, "verilog", "work")]
edifs = platform.edifs edifs = platform.edifs
ips = platform.ips ips = platform.ips
self._build_batch(platform, sources, edifs, ips, build_name) self._build_batch(platform, sources, edifs, ips, build_name)