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bus/csr: Rename a->adr d->dat to be consistent with the other buses

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Sebastien Bourdeauducq 2012-02-13 21:46:39 +01:00
parent d6da88d11d
commit 8a61d9d121
3 changed files with 22 additions and 22 deletions
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22
migen/bank/csrgen.py
View file

@ -13,7 +13,7 @@ class Bank:
sync = [] sync = []
sel = Signal() sel = Signal()
comb.append(sel.eq(self.interface.a_i[9:] == Constant(self.address, BV(5)))) comb.append(sel.eq(self.interface.adr_i[9:] == Constant(self.address, BV(5))))
desc_exp = expand_description(self.description, 8) desc_exp = expand_description(self.description, 8)
nbits = bits_for(len(desc_exp)-1) nbits = bits_for(len(desc_exp)-1)
@ -22,29 +22,29 @@ class Bank:
bwcases = [] bwcases = []
for i, reg in enumerate(desc_exp): for i, reg in enumerate(desc_exp):
if isinstance(reg, RegisterRaw): if isinstance(reg, RegisterRaw):
comb.append(reg.r.eq(self.interface.d_i[:reg.size])) comb.append(reg.r.eq(self.interface.dat_i[:reg.size]))
comb.append(reg.re.eq(sel & \ comb.append(reg.re.eq(sel & \
self.interface.we_i & \ self.interface.we_i & \
(self.interface.a_i[:nbits] == Constant(i, BV(nbits))))) (self.interface.adr_i[:nbits] == Constant(i, BV(nbits)))))
elif isinstance(reg, RegisterFields): elif isinstance(reg, RegisterFields):
bwra = [Constant(i, BV(nbits))] bwra = [Constant(i, BV(nbits))]
offset = 0 offset = 0
for field in reg.fields: for field in reg.fields:
if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE: if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
bwra.append(field.storage.eq(self.interface.d_i[offset:offset+field.size])) bwra.append(field.storage.eq(self.interface.dat_i[offset:offset+field.size]))
offset += field.size offset += field.size
if len(bwra) > 1: if len(bwra) > 1:
bwcases.append(bwra) bwcases.append(bwra)
else: else:
raise TypeError raise TypeError
if bwcases: if bwcases:
sync.append(If(sel & self.interface.we_i, Case(self.interface.a_i[:nbits], *bwcases))) sync.append(If(sel & self.interface.we_i, Case(self.interface.adr_i[:nbits], *bwcases)))
# Bus reads # Bus reads
brcases = [] brcases = []
for i, reg in enumerate(desc_exp): for i, reg in enumerate(desc_exp):
if isinstance(reg, RegisterRaw): if isinstance(reg, RegisterRaw):
brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(reg.w)]) brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(reg.w)])
elif isinstance(reg, RegisterFields): elif isinstance(reg, RegisterFields):
brs = [] brs = []
reg_readable = False reg_readable = False
@ -56,16 +56,16 @@ class Bank:
brs.append(Constant(0, BV(field.size))) brs.append(Constant(0, BV(field.size)))
if reg_readable: if reg_readable:
if len(brs) > 1: if len(brs) > 1:
brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(Cat(*brs))]) brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(Cat(*brs))])
else: else:
brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])]) brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(brs[0])])
else: else:
raise TypeError raise TypeError
if brcases: if brcases:
sync.append(self.interface.d_o.eq(Constant(0, BV(8)))) sync.append(self.interface.dat_o.eq(Constant(0, BV(8))))
sync.append(If(sel, Case(self.interface.a_i[:nbits], *brcases))) sync.append(If(sel, Case(self.interface.adr_i[:nbits], *brcases)))
else: else:
comb.append(self.interface.d_o.eq(Constant(0, BV(8)))) comb.append(self.interface.dat_o.eq(Constant(0, BV(8))))
# Device access # Device access
for reg in self.description: for reg in self.description:

14
migen/bus/csr.py
View file

@ -3,10 +3,10 @@ from migen.corelogic.misc import optree
from migen.bus.simple import Simple from migen.bus.simple import Simple
_desc = [ _desc = [
(True, "a", 14), (True, "adr", 14),
(True, "we", 1), (True, "we", 1),
(True, "d", 8), (True, "dat", 8),
(False, "d", 8) (False, "dat", 8)
] ]
class Master(Simple): class Master(Simple):
@ -25,9 +25,9 @@ class Interconnect:
def get_fragment(self): def get_fragment(self):
comb = [] comb = []
for slave in self.slaves: for slave in self.slaves:
comb.append(slave.a_i.eq(self.master.a_o)) comb.append(slave.adr_i.eq(self.master.adr_o))
comb.append(slave.we_i.eq(self.master.we_o)) comb.append(slave.we_i.eq(self.master.we_o))
comb.append(slave.d_i.eq(self.master.d_o)) comb.append(slave.dat_i.eq(self.master.dat_o))
rb = optree('|', [slave.d_o for slave in self.slaves]) rb = optree("|", [slave.dat_o for slave in self.slaves])
comb.append(self.master.d_i.eq(rb)) comb.append(self.master.dat_i.eq(rb))
return Fragment(comb) return Fragment(comb)

8
migen/bus/wishbone2csr.py
View file

@ -3,7 +3,7 @@ from migen.bus import csr
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.corelogic import timeline from migen.corelogic import timeline
class WB2CSR(): class WB2CSR:
def __init__(self): def __init__(self):
self.wishbone = wishbone.Slave() self.wishbone = wishbone.Slave()
self.csr = csr.Master() self.csr = csr.Master()
@ -15,8 +15,8 @@ class WB2CSR():
def get_fragment(self): def get_fragment(self):
sync = [ sync = [
self.csr.we_o.eq(0), self.csr.we_o.eq(0),
self.csr.d_o.eq(self.wishbone.dat_i[:8]), self.csr.dat_o.eq(self.wishbone.dat_i[:8]),
self.csr.a_o.eq(self.wishbone.adr_i[:14]), self.csr.adr_o.eq(self.wishbone.adr_i[:14]),
self.wishbone.dat_o.eq(self.csr.d_i) self.wishbone.dat_o.eq(self.csr.dat_i)
] ]
return Fragment(sync=sync) + self.timeline.get_fragment() return Fragment(sync=sync) + self.timeline.get_fragment()