software/liblitedram/accessors: Add seperators to improve readability.
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@ -4,6 +4,10 @@
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#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
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/*----------------------------------------------------------------------------*/
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/* Read DQ Delays Reset/Increment Functions */
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/*----------------------------------------------------------------------------*/
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#if defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
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int read_dq_delay[SDRAM_PHY_MODULES];
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@ -21,6 +25,10 @@ void read_rst_dq_delay(int module) {
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#endif // defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
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/*----------------------------------------------------------------------------*/
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/* Write DQ/DQS/Clk Delays Reset/Increment Functions */
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/*----------------------------------------------------------------------------*/
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#if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
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int sdram_clock_delay;
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@ -94,6 +102,10 @@ void write_rst_delay(int module) {
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#endif // defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
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/*----------------------------------------------------------------------------*/
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/* Bitslip Delays Reset/Increment Functions */
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/*----------------------------------------------------------------------------*/
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#if defined(SDRAM_PHY_BITSLIPS)
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int read_dq_bitslip[SDRAM_PHY_MODULES];
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@ -124,6 +136,10 @@ void write_rst_dq_bitslip(int module) {
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#endif // defined(SDRAM_PHY_BITSLIPS)
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/*----------------------------------------------------------------------------*/
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/* SDRAM Module Selection Functions */
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/*----------------------------------------------------------------------------*/
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void sdram_select(int module, int dq_line) {
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ddrphy_dly_sel_write(1 << module);
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@ -148,6 +164,10 @@ void sdram_deselect(int module, int dq_line) {
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#endif
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}
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/*----------------------------------------------------------------------------*/
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/* SDRAM Actions */
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/*----------------------------------------------------------------------------*/
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void sdram_leveling_action(int module, int dq_line, action_callback action) {
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/* Select module */
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sdram_select(module, dq_line);
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@ -11,6 +11,10 @@ extern "C" {
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typedef void (*action_callback)(int module);
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/*----------------------------------------------------------------------------*/
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/* Read DQ Delays Reset/Increment Functions */
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/*----------------------------------------------------------------------------*/
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#if defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
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extern int read_dq_delay[SDRAM_PHY_MODULES];
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@ -19,6 +23,11 @@ void read_rst_dq_delay(int module);
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#endif // defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
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/*----------------------------------------------------------------------------*/
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/* Write DQ/DQS/Clk Delays Reset/Increment Functions */
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/*----------------------------------------------------------------------------*/
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#if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
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extern int sdram_clock_delay;
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@ -37,6 +46,10 @@ void write_rst_delay(int module);
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#endif // defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
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/*----------------------------------------------------------------------------*/
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/* Bitslip Delays Reset/Increment Functions */
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/*----------------------------------------------------------------------------*/
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#if defined(SDRAM_PHY_BITSLIPS)
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extern int read_dq_bitslip[SDRAM_PHY_MODULES];
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@ -49,8 +62,17 @@ void write_rst_dq_bitslip(int module);
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#endif // defined(SDRAM_PHY_BITSLIPS)
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/*----------------------------------------------------------------------------*/
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/* SDRAM Module Selection Functions */
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/*----------------------------------------------------------------------------*/
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void sdram_select(int module, int dq_line);
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void sdram_deselect(int module, int dq_line);
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/*----------------------------------------------------------------------------*/
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/* SDRAM Actions */
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/*----------------------------------------------------------------------------*/
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void sdram_leveling_action(int module, int dq_line, action_callback action);
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#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
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