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gensoc: simplify WB address decoding

This commit is contained in:
Sebastien Bourdeauducq 2014-11-30 22:05:51 +08:00
parent 4189440eef
commit 8ae3a00a94
1 changed files with 4 additions and 4 deletions
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8
misoclib/gensoc/__init__.py
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@ -59,7 +59,7 @@ class GenSoC(Module):
self._wb_masters = [self.cpu.ibus, self.cpu.dbus] self._wb_masters = [self.cpu.ibus, self.cpu.dbus]
self._wb_slaves = [ self._wb_slaves = [
(lambda a: a[26:29] == 1, self.sram.bus), (lambda a: a[26:29] == 1, self.sram.bus),
(lambda a: a[27:29] == 3, self.wishbone2csr.wishbone) (lambda a: a[26:29] == 6, self.wishbone2csr.wishbone)
] ]
self.add_cpu_memory_region("sram", 0x10000000, sram_size) self.add_cpu_memory_region("sram", 0x10000000, sram_size)
@ -173,7 +173,7 @@ class SDRAMSoC(GenSoC):
# Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000) # Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000)
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master()) self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
self.add_wb_slave(lambda a: a[27:29] == 2, self.wishbone2lasmi.wishbone) self.add_wb_slave(lambda a: a[26:29] == 4, self.wishbone2lasmi.wishbone)
self.add_cpu_memory_region("sdram", 0x40000000, self.add_cpu_memory_region("sdram", 0x40000000,
2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8) 2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8)
elif self.ramcon_type == "minicon": elif self.ramcon_type == "minicon":
@ -182,11 +182,11 @@ class SDRAMSoC(GenSoC):
sdram_width = flen(sdramcon.bus.dat_r) sdram_width = flen(sdramcon.bus.dat_r)
if (sdram_width == 32): if (sdram_width == 32):
self.add_wb_slave(lambda a: a[27:29] == 2, sdramcon.bus) self.add_wb_slave(lambda a: a[26:29] == 4, sdramcon.bus)
elif (sdram_width < 32): elif (sdram_width < 32):
self.submodules.dc = dc = wishbone.DownConverter(32, sdram_width) self.submodules.dc = dc = wishbone.DownConverter(32, sdram_width)
self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus) self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus)
self.add_wb_slave(lambda a: a[27:29] == 2, dc.wishbone_i) self.add_wb_slave(lambda a: a[26:29] == 4, dc.wishbone_i)
else: else:
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))