clean up TestDesign
This commit is contained in:
Florent Kermarrec
parent
7df1d75dee
commit
8b1522bbc9
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@ -8,7 +8,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from miscope import MiLa, Term, UART2Wishbone
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from miscope.uart2wishbone import UART2Wishbone
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from misoclib import identifier
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from lib.sata.common import *
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@ -128,17 +127,18 @@ class SimDesign(UART2WB):
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self.sata_phy_device.sink.charisk.eq(0b0001)
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]
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class ClockLeds(Module):
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def __init__(self, platform):
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led_sata_rx = platform.request("user_led", 0)
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led_sata_tx = platform.request("user_led", 1)
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class DebugLeds(Module):
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def __init__(self, platform, sata_phy):
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# blinking leds (sata_rx and sata_tx clocks)
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sata_rx_led = platform.request("user_led", 0)
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sata_tx_led = platform.request("user_led", 1)
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sata_rx_cnt = Signal(32)
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sata_tx_cnt = Signal(32)
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self.sync.sata_rx += \
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If(sata_rx_cnt == 0,
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led_sata_rx.eq(~led_sata_rx),
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sata_rx_led.eq(~sata_rx_led),
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sata_rx_cnt.eq(150*1000*1000//2)
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).Else(
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sata_rx_cnt.eq(sata_rx_cnt-1)
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@ -146,18 +146,21 @@ class ClockLeds(Module):
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self.sync.sata_tx += \
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If(sata_tx_cnt == 0,
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led_sata_tx.eq(~led_sata_tx),
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sata_tx_led.eq(~sata_tx_led),
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sata_tx_cnt.eq(150*1000*1000//2)
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).Else(
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sata_tx_cnt.eq(sata_tx_cnt-1)
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)
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# ready leds (crg and ctrl)
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self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready)
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self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready)
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class TestDesign(UART2WB, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"mila": 10,
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"command_generator": 11,
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"bist": 12
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"sata_bist": 10,
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"mila": 11
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}
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csr_map.update(UART2WB.csr_map)
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@ -168,27 +171,12 @@ class TestDesign(UART2WB, AutoCSR):
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self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, speed="SATA2")
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self.sata_con = SATACON(self.sata_phy)
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self.sata_bist = SATABIST(self.sata_con)
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self.bist = SATABIST(self.sata_con)
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self.clock_leds = ClockLeds(platform)
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self.comb += platform.request("user_led", 2).eq(self.sata_phy.crg.ready)
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self.comb += platform.request("user_led", 3).eq(self.sata_phy.ctrl.ready)
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ctrl = self.sata_phy.ctrl
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self.command_tx_fsm_state = Signal(4)
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self.transport_tx_fsm_state = Signal(4)
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self.link_tx_fsm_state = Signal(4)
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self.command_rx_fsm_state = Signal(4)
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self.command_rx_out_fsm_state = Signal(4)
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self.transport_rx_fsm_state = Signal(4)
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self.link_rx_fsm_state = Signal(4)
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self.leds = DebugLeds(platform, self.sata_phy)
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debug = (
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ctrl.ready,
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self.sata_phy.ctrl.ready,
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self.sata_phy.source.stb,
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self.sata_phy.source.data,
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@ -218,7 +206,6 @@ class TestDesign(UART2WB, AutoCSR):
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self.mila = MiLa(depth=2048, dat=Cat(*debug))
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self.mila.add_port(Term)
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if export_mila:
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mila_filename = os.path.join(platform.soc_ext_path, "test", "mila.csv")
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self.mila.export(self, debug, mila_filename)
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22
test/bist.py
22
test/bist.py
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@ -14,28 +14,28 @@ class SATABISTDriver:
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def set_mode(self, mode):
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self.mode = mode
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self.regs.bist_write_only.write(0)
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self.regs.bist_read_only.write(0)
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self.regs.sata_bist_write_only.write(0)
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self.regs.sata_bist_read_only.write(0)
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if mode == "wr":
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self.regs.bist_write_only.write(1)
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self.regs.sata_bist_write_only.write(1)
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if mode == "rd":
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self.regs.bist_read_only.write(1)
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self.regs.sata_bist_read_only.write(1)
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def start(self, sector, count, mode):
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self.set_mode(mode)
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self.regs.bist_start_sector.write(sector)
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self.regs.bist_count.write(count)
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self.regs.bist_stop.write(0)
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self.regs.bist_start.write(1)
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self.regs.sata_bist_start_sector.write(sector)
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self.regs.sata_bist_count.write(count)
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self.regs.sata_bist_stop.write(0)
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self.regs.sata_bist_start.write(1)
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def stop(self):
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self.regs.bist_stop.write(1)
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self.regs.sata_bist_stop.write(1)
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def show_status(self):
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errors = self.regs.bist_errors.read() - self.last_errors
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errors = self.regs.sata_bist_errors.read() - self.last_errors
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self.last_errors += errors
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sector = self.regs.bist_sector.read()
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sector = self.regs.sata_bist_sector.read()
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n = sector - self.last_sector
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self.last_sector = sector
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