hdd: rearrange code (will be easier to understand)
This commit is contained in:
Florent Kermarrec
parent
79e82d6ccd
commit
8b21e5fd21
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@ -93,10 +93,6 @@ class LinkPacket(list):
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self.append(dword)
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class LinkRXPacket(LinkPacket):
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def decode(self):
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self.descramble()
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return self.check_crc()
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def descramble(self):
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for i in range(len(self)):
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self[i] = self[i] ^ self.scrambled_datas[i]
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@ -114,15 +110,11 @@ class LinkRXPacket(LinkPacket):
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self.pop()
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return r
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def decode(self):
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self.descramble()
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return self.check_crc()
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class LinkTXPacket(LinkPacket):
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def encode(self):
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self.insert_crc()
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self.scramble()
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def scramble(self):
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for i in range(len(self)):
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self[i] = self[i] ^ self.scrambled_datas[i]
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def insert_crc(self):
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stdin = ""
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for v in self:
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@ -134,6 +126,14 @@ class LinkTXPacket(LinkPacket):
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crc = int(out.decode("ASCII"), 16)
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self.append(crc)
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def scramble(self):
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for i in range(len(self)):
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self[i] = self[i] ^ self.scrambled_datas[i]
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def encode(self):
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self.insert_crc()
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self.scramble()
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class LinkLayer(Module):
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def __init__(self, phy, debug=False, random_level=0):
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self.phy = phy
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@ -159,46 +159,6 @@ class LinkLayer(Module):
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def set_transport_callback(self, callback):
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self.transport_callback = callback
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def remove_cont(self, dword):
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if dword == primitives["HOLD"]:
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if self.rx_cont:
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self.tx_lasts = [0, 0, 0]
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if dword == primitives["CONT"]:
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self.rx_cont = True
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elif is_primitive(dword):
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self.rx_last = dword
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self.rx_cont = False
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if self.rx_cont:
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dword = self.rx_last
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return dword
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def callback(self, dword):
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if dword == primitives["X_RDY"]:
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self.phy.send(primitives["R_RDY"])
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elif dword == primitives["WTRM"]:
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self.phy.send(primitives["R_OK"])
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if self.rx_packet.ongoing:
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self.rx_packet.decode()
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if self.transport_callback is not None:
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self.transport_callback(self.rx_packet)
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self.rx_packet.ongoing = False
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elif dword == primitives["HOLD"]:
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self.phy.send(primitives["HOLDA"])
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elif dword == primitives["EOF"]:
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pass
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elif self.rx_packet.ongoing:
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if dword != primitives["HOLD"]:
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n = randn(100)
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if n < self.random_level:
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self.phy.send(primitives["HOLD"])
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else:
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self.phy.send(primitives["R_IP"])
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if not is_primitive(dword):
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self.rx_packet.append(dword)
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elif dword == primitives["SOF"]:
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self.rx_packet = LinkRXPacket()
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self.rx_packet.ongoing = True
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def send(self, dword):
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if self.send_state == "RDY":
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self.phy.send(primitives["X_RDY"])
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@ -243,6 +203,46 @@ class LinkLayer(Module):
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else:
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self.tx_cont_nb = 0
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def remove_cont(self, dword):
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if dword == primitives["HOLD"]:
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if self.rx_cont:
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self.tx_lasts = [0, 0, 0]
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if dword == primitives["CONT"]:
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self.rx_cont = True
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elif is_primitive(dword):
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self.rx_last = dword
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self.rx_cont = False
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if self.rx_cont:
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dword = self.rx_last
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return dword
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def callback(self, dword):
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if dword == primitives["X_RDY"]:
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self.phy.send(primitives["R_RDY"])
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elif dword == primitives["WTRM"]:
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self.phy.send(primitives["R_OK"])
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if self.rx_packet.ongoing:
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self.rx_packet.decode()
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if self.transport_callback is not None:
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self.transport_callback(self.rx_packet)
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self.rx_packet.ongoing = False
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elif dword == primitives["HOLD"]:
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self.phy.send(primitives["HOLDA"])
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elif dword == primitives["EOF"]:
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pass
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elif self.rx_packet.ongoing:
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if dword != primitives["HOLD"]:
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n = randn(100)
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if n < self.random_level:
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self.phy.send(primitives["HOLD"])
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else:
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self.phy.send(primitives["R_IP"])
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if not is_primitive(dword):
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self.rx_packet.append(dword)
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elif dword == primitives["SOF"]:
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self.rx_packet = LinkRXPacket()
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self.rx_packet.ongoing = True
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def gen_simulation(self, selfp):
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self.tx_packet.done = True
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self.phy.send(primitives["SYNC"])
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@ -443,6 +443,27 @@ class HDD(Module):
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self.wr_length = 0
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self.wr_cnt = 0
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def allocate_mem(self, base, length):
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if self.mem_debug:
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print("[HDD] : Allocating {n} bytes at 0x{a}".format(n=length, a=base))
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self.mem = HDDMemRegion(base, length)
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def write_mem(self, adr, data):
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if self.mem_debug:
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print("[HDD] : Writing {n} bytes at 0x{a}".format(n=len(data)*4, a=adr))
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current_adr = (adr-self.mem.base)//4
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for i in range(len(data)):
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self.mem.data[current_adr+i] = data[i]
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def read_mem(self, adr, length=1):
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if self.mem_debug:
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print("[HDD] : Reading {n} bytes at 0x{a}".format(n=length, a=adr))
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current_adr = (adr-self.mem.base)//4
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data = []
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for i in range(length//4):
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data.append(self.mem.data[current_adr+i])
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return data
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def write_dma_cmd(self, fis):
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self.wr_address = fis.lba_lsb
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self.wr_length = fis.count
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@ -466,24 +487,3 @@ class HDD(Module):
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return [FIS_REG_D2H()]
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else:
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return None
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def allocate_mem(self, base, length):
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if self.mem_debug:
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print("[HDD] : Allocating {n} bytes at 0x{a}".format(n=length, a=base))
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self.mem = HDDMemRegion(base, length)
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def write_mem(self, adr, data):
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if self.mem_debug:
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print("[HDD] : Writing {n} bytes at 0x{a}".format(n=len(data)*4, a=adr))
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current_adr = (adr-self.mem.base)//4
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for i in range(len(data)):
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self.mem.data[current_adr+i] = data[i]
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def read_mem(self, adr, length=1):
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if self.mem_debug:
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print("[HDD] : Reading {n} bytes at 0x{a}".format(n=length, a=adr))
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current_adr = (adr-self.mem.base)//4
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data = []
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for i in range(length//4):
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data.append(self.mem.data[current_adr+i])
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return data
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