cores/xadc: Re-arrange and simplify code a bit.
This commit is contained in:
parent
92032b446c
commit
8b36649c89
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@ -2,7 +2,7 @@
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# This file is part of LiteX.
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# This file is part of LiteX.
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#
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#
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# Copyright (c) 2014-2015 Robert Jordens <jordens@gmail.com>
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# Copyright (c) 2014-2015 Robert Jordens <jordens@gmail.com>
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# Copyright (c) 2019-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019-2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019 bunnie <bunnie@kosagi.com>
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# Copyright (c) 2019 bunnie <bunnie@kosagi.com>
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# Copyright (c) 2021 Vamsi K Vytla <vamsi.vytla@gmail.com>
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# Copyright (c) 2021 Vamsi K Vytla <vamsi.vytla@gmail.com>
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# Copyright (c) 2022 Sylvain Munaut <tnt@246tNt.com>
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# Copyright (c) 2022 Sylvain Munaut <tnt@246tNt.com>
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@ -10,15 +10,28 @@
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from migen import *
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from migen import *
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from litex.gen import LiteXModule
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr import *
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# Layouts -----------------------------------------------------------------------------------------
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# Layouts -----------------------------------------------------------------------------------------
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analog_layout = [("vauxp", 16), ("vauxn", 16), ("vp", 1), ("vn", 1)]
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analog_layout = [("vauxp", 16), ("vauxn", 16), ("vp", 1), ("vn", 1)]
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# Xilinx System Monitor DRP ------------------------------------------------------------------------
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# Xilinx System Monitor ----------------------------------------------------------------------------
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class XilinxSystemMonitorChannel:
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def __init__(self, name, addr, bits, desc):
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self.name = name
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self.addr = addr
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self.bits = bits
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self.desc = "\n".join(desc) if isinstance(desc, list) else desc
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class XilinxSystemMonitor(LiteXModule):
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def add_channel(self, channel):
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setattr(self, channel.name, CSRStatus(channel.bits, name=channel.name, description=channel.desc))
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channel.status = getattr(self, channel.name).status
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class SystemMonitorDRP(Module, AutoCSR):
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def expose_drp(self):
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def expose_drp(self):
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self.drp_enable = CSRStorage() # Set to 1 to use DRP and disable auto-sampling.
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self.drp_enable = CSRStorage() # Set to 1 to use DRP and disable auto-sampling.
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self.drp_read = CSR()
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self.drp_read = CSR()
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@ -53,21 +66,30 @@ class SystemMonitorDRP(Module, AutoCSR):
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# Xilinx 7-Series System Monitor -------------------------------------------------------------------
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# Xilinx 7-Series System Monitor -------------------------------------------------------------------
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class S7SystemMonitor(SystemMonitorDRP, AutoCSR):
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S7SystemMonitorChannels = [
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dadr_size = 7
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XilinxSystemMonitorChannel(name="temperature", addr=0x0, bits=12, desc=[
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"Raw Temperature value from XADC.",
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"Temperature (°C) = ``Value`` x 503.975 / 4096 - 273.15.",
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]),
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XilinxSystemMonitorChannel(name="vccint", addr=0x1, bits=12, desc=[
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"Raw VCCINT value from XADC.",
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"VCCINT (V) = ``Value`` x 3 / 4096.",
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]),
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XilinxSystemMonitorChannel(name="vccaux", addr=0x2, bits=12, desc=[
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"Raw VCCAUX value from XADC.",
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"VCCAUX (V) = ``Value`` x 3 / 4096.",
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]),
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XilinxSystemMonitorChannel(name="vccbram", addr=0x6, bits=12, desc=[
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"Raw VCCBRAM value from XADC.",
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"VCCBRAM (V) = ``Value`` x 3 / 4096.",
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]),
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]
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def __init__(self, analog_pads=None):
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class S7SystemMonitor(XilinxSystemMonitor):
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# Temperature
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def __init__(self, channels=S7SystemMonitorChannels, analog_pads=None):
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self.temperature = CSRStatus(12, description="""Raw Temperature value from XADC.\n
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# Channels.
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Temperature (°C) = ``Value`` x 503.975 / 4096 - 273.15.""")
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for channel in channels:
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self.add_channel(channel)
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# Voltages
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self.vccint = CSRStatus(12, description="""Raw VCCINT value from XADC.\n
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VCCINT (V) = ``Value`` x 3 / 4096.""")
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self.vccaux = CSRStatus(12, description="""Raw VCCAUX value from XADC.\n
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VCCAUX (V) = ``Value`` x 3 / 4096.""")
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self.vccbram = CSRStatus(12, description="""Raw VCCBRAM value from XADC.\n
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VCCBRAM (V) = ``Value`` x 3 / 4096.""")
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# End of Convertion/Sequence
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# End of Convertion/Sequence
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self.eoc = CSRStatus(description="End of Convertion Status, ``1``: Convertion Done.")
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self.eoc = CSRStatus(description="End of Convertion Status, ``1``: Convertion Done.")
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@ -94,16 +116,16 @@ class S7SystemMonitor(SystemMonitorDRP, AutoCSR):
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self.drp_en = Signal()
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self.drp_en = Signal()
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self.specials += Instance("XADC",
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self.specials += Instance("XADC",
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# From UG480
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# From UG480
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p_INIT_40=0x9000, p_INIT_41=0x2ef0, p_INIT_42=0x0400,
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p_INIT_40 = 0x9000, p_INIT_41 = 0x2ef0, p_INIT_42 = 0x0400,
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p_INIT_48=0x4701, p_INIT_49=0x000f,
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p_INIT_48 = 0x4701, p_INIT_49 = 0x000f,
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p_INIT_4A=0x4700, p_INIT_4B=0x0000,
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p_INIT_4A = 0x4700, p_INIT_4B = 0x0000,
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p_INIT_4C=0x0000, p_INIT_4D=0x0000,
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p_INIT_4C = 0x0000, p_INIT_4D = 0x0000,
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p_INIT_4E=0x0000, p_INIT_4F=0x0000,
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p_INIT_4E = 0x0000, p_INIT_4F = 0x0000,
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p_INIT_50=0xb5ed, p_INIT_51=0x5999,
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p_INIT_50 = 0xb5ed, p_INIT_51 = 0x5999,
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p_INIT_52=0xa147, p_INIT_53=0xdddd,
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p_INIT_52 = 0xa147, p_INIT_53 = 0xdddd,
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p_INIT_54=0xa93a, p_INIT_55=0x5111,
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p_INIT_54 = 0xa93a, p_INIT_55 = 0x5111,
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p_INIT_56=0x91eb, p_INIT_57=0xae4e,
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p_INIT_56 = 0x91eb, p_INIT_57 = 0xae4e,
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p_INIT_58=0x5999, p_INIT_5C=0x5111,
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p_INIT_58 = 0x5999, p_INIT_5C = 0x5111,
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o_ALM = self.alarm,
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o_ALM = self.alarm,
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o_OT = self.ot,
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o_OT = self.ot,
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o_BUSY = busy,
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o_BUSY = busy,
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@ -116,8 +138,8 @@ class S7SystemMonitor(SystemMonitorDRP, AutoCSR):
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i_VN = 0 if analog_pads is None else analog_pads.vn,
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i_VN = 0 if analog_pads is None else analog_pads.vn,
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i_CONVST = 0,
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i_CONVST = 0,
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i_CONVSTCLK = 0,
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i_CONVSTCLK = 0,
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i_RESET = ResetSignal(),
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i_RESET = ResetSignal("sys"),
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i_DCLK = ClockSignal(),
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i_DCLK = ClockSignal("sys"),
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i_DWE = self.dwe,
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i_DWE = self.dwe,
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i_DEN = self.den,
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i_DEN = self.den,
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o_DRDY = self.drdy,
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o_DRDY = self.drdy,
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@ -125,45 +147,54 @@ class S7SystemMonitor(SystemMonitorDRP, AutoCSR):
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i_DI = self.di,
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i_DI = self.di,
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o_DO = self.do
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o_DO = self.do
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)
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)
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self.comb += [
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If(~self.drp_en,
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# DRP.
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self.comb += If(~self.drp_en,
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self.den.eq(eoc),
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self.den.eq(eoc),
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self.dadr.eq(channel),
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self.dadr.eq(channel),
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)
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)
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]
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# Channels update.
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# Channels update.
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channels = {
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channel_cases = dict(zip(
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0x0 : self.temperature,
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[c.addr for c in channels],
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0x1 : self.vccint,
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[c.status.eq(self.do >> 4) for c in channels],
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0x2 : self.vccaux,
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))
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0x6 : self.vccbram
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self.sync += If(self.drdy, Case(channel, channel_cases))
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}
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self.sync += [
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If(self.drdy,
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Case(channel, dict(
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(k, v.status.eq(self.do >> 4))
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for k, v in channels.items()))
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)
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]
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# End of Convertion/Sequence update.
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# End of Conversion/Sequence update.
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self.sync += [
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self.sync += [
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self.eoc.status.eq((self.eoc.status & ~self.eoc.we) | eoc),
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self.eoc.status.eq((self.eoc.status & ~self.eoc.we) | eoc),
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self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
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self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
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]
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]
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class XADC(S7SystemMonitor): pass
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class XADC(S7SystemMonitor): pass # For compat.
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# Xilinx Ultrascale System Monitor -----------------------------------------------------------------
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# Xilinx Ultrascale System Monitor -----------------------------------------------------------------
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class USFamilySystemMonitor(SystemMonitorDRP, AutoCSR):
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USSystemMonitorChannels = [
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dadr_size = 8
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XilinxSystemMonitorChannel(name="temperature", addr=0x0, bits=10, desc=[
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"Raw Temperature value from SYSMONE1.",
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"Temperature (°C) = ``Value`` x 503.975 / 1024 - 273.15.",
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]),
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XilinxSystemMonitorChannel(name="vccint", addr=0x1, bits=10, desc=[
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"Raw VCCINT value from SYSMONE1.",
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"VCCINT (V) = ``Value`` x 3 / 1024.",
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]),
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XilinxSystemMonitorChannel(name="vccaux", addr=0x2, bits=10, desc=[
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"Raw VCCAUX value from SYSMONE1.",
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"VCCAUX (V) = ``Value`` x 3 / 1024.",
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]),
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XilinxSystemMonitorChannel(name="vccbram", addr=0x6, bits=10, desc=[
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"Raw VCCBRAM value from SYSMONE1.",
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"VCCBRAM (V) = ``Value`` x 3 / 1024.",
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]),
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]
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def __init__(self, analog_pads=None):
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class USSystemMonitor(XilinxSystemMonitor):
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# Channels CSRs
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def __init__(self, channels=USSystemMonitorChannels, primitive="SYSMONE1", sim_device="ULTRASCALE", analog_pads=None):
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for reg_addr, name, desc in self._channels:
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# Channels.
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setattr(self, name, CSRStatus(10, name=name, description=desc))
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for channel in channels:
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self.add_channel(channel)
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# End of Convertion/Sequence
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# End of Convertion/Sequence
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self.eoc = CSRStatus(description="End of Conversion Status, ``1``: Conversion Done.")
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self.eoc = CSRStatus(description="End of Conversion Status, ``1``: Conversion Done.")
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@ -176,31 +207,33 @@ class USFamilySystemMonitor(SystemMonitorDRP, AutoCSR):
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# # #
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# # #
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busy = Signal()
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busy = Signal()
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channel = Signal(self.dadr_size)
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channel = Signal(8)
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eoc = Signal()
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eoc = Signal()
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eos = Signal()
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eos = Signal()
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# SYSMONE1 instance ------------------------------------------------------------------------
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# SYSMOM instance.
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self.dwe = Signal()
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self.dwe = Signal()
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self.den = Signal()
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self.den = Signal()
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self.drdy = Signal()
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self.drdy = Signal()
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self.dadr = Signal(self.dadr_size)
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self.dadr = Signal(8)
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self.di = Signal(16)
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self.di = Signal(16)
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self.do = Signal(16)
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self.do = Signal(16)
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self.drp_en = Signal()
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self.drp_en = Signal()
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self.params = dict()
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params = dict(
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if sim_device is not None:
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self.params.update(p_SIM_DEVICE=sim_device)
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self.params.update(
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# From UG580
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# From UG580
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p_INIT_40=0x9000, p_INIT_41=0x2fd0, p_INIT_42=0x1000,
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p_INIT_40 = 0x9000, p_INIT_41 = 0x2fd0, p_INIT_42 = 0x1000,
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p_INIT_46=0x000f, p_INIT_48=0x4701, p_INIT_49=0x000f,
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p_INIT_46 = 0x000f, p_INIT_48 = 0x4701, p_INIT_49 = 0x000f,
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p_INIT_47=0x000f, p_INIT_4A=0x47e0, p_INIT_4B=0x0000,
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p_INIT_47 = 0x000f, p_INIT_4A = 0x47e0, p_INIT_4B = 0x0000,
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p_INIT_4C=0x0000, p_INIT_4D=0x0000,
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p_INIT_4C = 0x0000, p_INIT_4D = 0x0000,
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p_INIT_4E=0x0000, p_INIT_4F=0x0000,
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p_INIT_4E = 0x0000, p_INIT_4F = 0x0000,
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p_INIT_50=0xb5ed, p_INIT_51=0x5999,
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p_INIT_50 = 0xb5ed, p_INIT_51 = 0x5999,
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p_INIT_52=0xa147, p_INIT_53=0xdddd,
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p_INIT_52 = 0xa147, p_INIT_53 = 0xdddd,
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p_INIT_54=0xa93a, p_INIT_55=0x5111,
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p_INIT_54 = 0xa93a, p_INIT_55 = 0x5111,
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p_INIT_56=0x91eb, p_INIT_57=0xae4e,
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p_INIT_56 = 0x91eb, p_INIT_57 = 0xae4e,
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p_INIT_58=0x5999, p_INIT_5C=0x5111,
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p_INIT_58 = 0x5999, p_INIT_5C = 0x5111,
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o_ALM = self.alarm,
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o_ALM = self.alarm,
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o_OT = self.ot,
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o_OT = self.ot,
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o_BUSY = busy,
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o_BUSY = busy,
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@ -213,8 +246,8 @@ class USFamilySystemMonitor(SystemMonitorDRP, AutoCSR):
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i_VN = 0 if analog_pads is None else analog_pads.vn,
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i_VN = 0 if analog_pads is None else analog_pads.vn,
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i_CONVST = 0,
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i_CONVST = 0,
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i_CONVSTCLK = 0,
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i_CONVSTCLK = 0,
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i_RESET = ResetSignal(),
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i_RESET = ResetSignal("sys"),
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i_DCLK = ClockSignal(),
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i_DCLK = ClockSignal("sys"),
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i_DWE = self.dwe,
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i_DWE = self.dwe,
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i_DEN = self.den,
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i_DEN = self.den,
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o_DRDY = self.drdy,
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o_DRDY = self.drdy,
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@ -222,25 +255,20 @@ class USFamilySystemMonitor(SystemMonitorDRP, AutoCSR):
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i_DI = self.di,
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i_DI = self.di,
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o_DO = self.do
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o_DO = self.do
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)
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)
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if self._sim_device is not None:
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self.specials += Instance(primitive, self.params)
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params['p_SIM_DEVICE'] = self._sim_device
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self.specials += Instance(self._block_name, **params)
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self.comb += [
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# DRP.
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If(~self.drp_en,
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self.comb += If(~self.drp_en,
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self.den.eq(eoc),
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self.den.eq(eoc),
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self.dadr.eq(channel),
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self.dadr.eq(channel),
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)
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)
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]
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# Channels update.
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# Channels update.
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self.sync += [
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channel_cases = dict(zip(
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If(self.drdy,
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[c.addr for c in channels],
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Case(channel, dict(
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[c.status.eq((self.do >> 6) & 0x3ff) for c in channels],
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(reg_addr, getattr(self, name).status.eq((self.do >> 6) & 0x3ff))
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))
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for reg_addr, name, desc in self._channels))
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self.sync += If(self.drdy, Case(channel, channel_cases))
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)
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]
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# End of Convertion/Sequence update.
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# End of Convertion/Sequence update.
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self.sync += [
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self.sync += [
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@ -248,55 +276,56 @@ class USFamilySystemMonitor(SystemMonitorDRP, AutoCSR):
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self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
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self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
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]
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]
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# Xilinx Ultrascale+ System Monitor -----------------------------------------------------------------
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# Xilinx Ultrascale Plus System Monitor ------------------------------------------------------------
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class USSystemMonitor(USFamilySystemMonitor):
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USPSystemMonitorChannels = [
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XilinxSystemMonitorChannel(name="temperature", addr=0x0, bits=10, desc=[
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"Raw Temperature value from SYSMONE4.",
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"Temperature (°C) = ``Value`` x 507.5921310 / 1024 - 279.42657680."
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]),
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XilinxSystemMonitorChannel(name="vccint", addr=0x1, bits=10, desc=[
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"Raw VCCINT value from SYSMONE4.",
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"VCCINT (V) = ``Value`` x 3 / 1024."
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]),
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XilinxSystemMonitorChannel(name="vccaux", addr=0x2, bits=10, desc=[
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"Raw VCCAUX value from SYSMONE4.",
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"VCCAUX (V) = ``Value`` x 3 / 1024."
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]),
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XilinxSystemMonitorChannel(name="vccbram", addr=0x6, bits=10, desc=[
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|
"Raw VCCBRAM value from SYSMONE4.",
|
||||||
|
"VCCBRAM (V) = ``Value`` x 3 / 1024."
|
||||||
|
]),
|
||||||
|
]
|
||||||
|
|
||||||
_block_name = 'SYSMONE1'
|
ZynqUSPSystemMonitorChannels = USPSystemMonitorChannels + [
|
||||||
_sim_device = None
|
XilinxSystemMonitorChannel(name="vccpsintlp", addr=0xd, bits=10, desc=[
|
||||||
_channels = [
|
"Raw VCCPSINTLP value from SYSMONE4.",
|
||||||
( 0x0, 'temperature',
|
"VCCPSINTLP (V) = ``Value`` x 3 / 1024.",
|
||||||
"Raw Temperature value from SYSMONE1.\n Temperature (°C) = ``Value`` x 503.975 / 1024 - 273.15."),
|
]),
|
||||||
( 0x1, 'vccint',
|
XilinxSystemMonitorChannel(name="vccpsintfp", addr=0xe, bits=10, desc=[
|
||||||
"Raw VCCINT value from SYSMONE1.\n VCCINT (V) = ``Value`` x 3 / 1024."),
|
"Raw VCCPSINTFP value from SYSMONE4.",
|
||||||
( 0x2, 'vccaux',
|
"VCCPSINTFP (V) = ``Value`` x 3 / 1024.",
|
||||||
"Raw VCCAUX value from SYSMONE1.\n VCCAUX (V) = ``Value`` x 3 / 1024."),
|
]),
|
||||||
( 0x6, 'vccbram',
|
XilinxSystemMonitorChannel(name="vccpsaux", addr=0xf, bits=10, desc=[
|
||||||
"Raw VCCBRAM value from SYSMONE1.\n VCCBRAM (V) = ``Value`` x 3 / 1024."),
|
"Raw VCCPSAUX value from SYSMONE4.",
|
||||||
]
|
"VCCPSAUX (V) = ``Value`` x 3 / 1024.",
|
||||||
|
]),
|
||||||
|
]
|
||||||
|
|
||||||
class USPSystemMonitor(USFamilySystemMonitor):
|
class USPSystemMonitor(USSystemMonitor):
|
||||||
|
def __init__(self, analog_pads=None):
|
||||||
|
USSystemMonitor.__init__(self,
|
||||||
|
channels = USPSystemMonitorChannels,
|
||||||
|
primitive = "SYSMONE4",
|
||||||
|
sim_device = "ULTRASCALE_PLUS",
|
||||||
|
analog_pads = analog_pads,
|
||||||
|
)
|
||||||
|
|
||||||
_block_name = 'SYSMONE4'
|
class ZyncUSPSystemMonitor(USSystemMonitor):
|
||||||
_sim_device = 'ULTRASCALE_PLUS'
|
def __init__(self, analog_pads=None):
|
||||||
_channels = [
|
USSystemMonitor.__init__(self,
|
||||||
( 0x0, 'temperature',
|
channels = ZyncUSPSystemMonitorChannels,
|
||||||
"Raw Temperature value from SYSMONE4.\n Temperature (°C) = ``Value`` x 507.5921310 / 1024 - 279.42657680."),
|
primitive = "SYSMONE4",
|
||||||
( 0x1, 'vccint',
|
sim_device = "ZYNQ_ULTRASCALE",
|
||||||
"Raw VCCINT value from SYSMONE4.\n VCCINT (V) = ``Value`` x 3 / 1024."),
|
analog_pads = analog_pads,
|
||||||
( 0x2, 'vccaux',
|
)
|
||||||
"Raw VCCAUX value from SYSMONE4.\n VCCAUX (V) = ``Value`` x 3 / 1024."),
|
|
||||||
( 0x6, 'vccbram',
|
|
||||||
"Raw VCCBRAM value from SYSMONE4.\n VCCBRAM (V) = ``Value`` x 3 / 1024."),
|
|
||||||
]
|
|
||||||
|
|
||||||
class ZynqUSPSystemMonitor(USFamilySystemMonitor):
|
|
||||||
|
|
||||||
_block_name = 'SYSMONE4'
|
|
||||||
_sim_device = 'ZYNQ_ULTRASCALE'
|
|
||||||
_channels = [
|
|
||||||
( 0x0, 'temperature',
|
|
||||||
"Raw Temperature value from SYSMONE4.\n Temperature (°C) = ``Value`` x 507.5921310 / 1024 - 279.42657680."),
|
|
||||||
( 0x1, 'vccint',
|
|
||||||
"Raw VCCINT value from SYSMONE4.\n VCCINT (V) = ``Value`` x 3 / 1024."),
|
|
||||||
( 0x2, 'vccaux',
|
|
||||||
"Raw VCCAUX value from SYSMONE4.\n VCCAUX (V) = ``Value`` x 3 / 1024."),
|
|
||||||
( 0x6, 'vccbram',
|
|
||||||
"Raw VCCBRAM value from SYSMONE4.\n VCCBRAM (V) = ``Value`` x 3 / 1024."),
|
|
||||||
( 0xd, 'vccpsintlp',
|
|
||||||
"Raw VCCPSINTLP value from SYSMONE4.\n VCCPSINTLP (V) = ``Value`` x 3 / 1024."),
|
|
||||||
( 0xe, 'vccpsintfp',
|
|
||||||
"Raw VCCPSINTFP value from SYSMONE4.\n VCCPSINTFP (V) = ``Value`` x 3 / 1024."),
|
|
||||||
( 0xf, 'vccpsaux',
|
|
||||||
"Raw VCCPSAUX value from SYSMONE4.\n VCCPSAUX (V) = ``Value`` x 3 / 1024."),
|
|
||||||
]
|
|
||||||
|
|
Loading…
Reference in New Issue