add phy_datapath_tb and start datapath simplification
This commit is contained in:
Florent Kermarrec
parent
9728a97834
commit
8bb40241fa
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@ -1,6 +1,7 @@
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from lib.sata.common import *
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from migen.genlib.misc import chooser
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from migen.flow.plumbing import Multiplexer, Demultiplexer
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class SATAPHYDatapathRX(Module):
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def __init__(self):
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@ -105,6 +106,52 @@ class SATAPHYDatapathTX(Module):
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chooser(fifo.source.charisk, mux, self.source.charisk)
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]
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class SATAPHYAlignInserter(Module):
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def __init__(self, ctrl):
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self.sink = sink = Sink(phy_description(32))
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self.source = source = Source(phy_description(32))
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###
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# send 2 ALIGN every 256 DWORDs
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# used for clock compensation between
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# HOST and device
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cnt = Signal(8)
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send = Signal()
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self.sync += \
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If(~ctrl.ready,
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cnt.eq(0)
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).Elif(source.stb & source.ack,
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cnt.eq(cnt+1)
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)
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self.comb += [
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send.eq(cnt < 2),
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If(send,
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source.stb.eq(1),
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source.charisk.eq(0b0001),
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source.data.eq(primitives["ALIGN"]),
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sink.ack.eq(0)
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).Else(
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source.stb.eq(sink.stb),
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source.data.eq(sink.data),
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source.charisk.eq(sink.charisk),
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sink.ack.eq(source.ack)
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)
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]
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class SATAPHYAlignRemover(Module):
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def __init__(self):
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self.sink = sink = Sink(phy_description(32))
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self.source = source = Source(phy_description(32))
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###
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charisk_match = sink.charisk == 0b0001
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data_match = sink.data == primitives["ALIGN"]
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self.comb += \
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If(sink.stb & charisk_match & data_match,
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sink.ack.eq(1),
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).Else(
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Record.connect(sink, source)
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)
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class SATAPHYDatapath(Module):
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def __init__(self, trx, ctrl):
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self.sink = Sink(phy_description(32))
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@ -112,61 +159,28 @@ class SATAPHYDatapath(Module):
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###
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# change data width & cross domain crossing
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rx = SATAPHYDatapathRX()
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tx = SATAPHYDatapathTX()
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self.submodules += rx, tx
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# TX path
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self.align_inserter = SATAPHYAlignInserter(ctrl)
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self.mux = Multiplexer(phy_description(32), 2)
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self.tx = SATAPHYDatapathTX()
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self.comb += [
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trx.source.connect(rx.sink),
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tx.source.connect(trx.sink)
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self.mux.sel.eq(ctrl.ready),
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Record.connect(self.sink, self.align_inserter.sink),
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Record.connect(ctrl.source, self.mux.sink0),
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Record.connect(self.align_inserter.source, self.mux.sink1),
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Record.connect(self.mux.source, self.tx.sink),
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Record.connect(self.tx.source, trx.sink)
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]
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# Align cnt (send 2 Align DWORDs every 256 DWORDs)
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align_cnt = Signal(8)
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self.sync += \
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If(~ctrl.ready,
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align_cnt.eq(0)
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).Elif(tx.sink.stb & tx.sink.ack,
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align_cnt.eq(align_cnt+1)
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)
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send_align = (align_cnt < 2)
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receive_align = Signal()
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self.comb += receive_align.eq(rx.source.stb &
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(rx.source.charisk == 0b0001) &
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(rx.source.data == primitives["ALIGN"]))
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# user / ctrl mux
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# RX path
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self.rx = SATAPHYDatapathRX()
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self.demux = Demultiplexer(phy_description(32), 2)
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self.align_remover = SATAPHYAlignRemover()
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self.comb += [
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# user
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If(ctrl.ready,
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If(send_align,
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tx.sink.stb.eq(1),
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tx.sink.data.eq(primitives["ALIGN"]),
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tx.sink.charisk.eq(0b0001),
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self.sink.ack.eq(0)
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).Else(
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tx.sink.stb.eq(self.sink.stb),
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tx.sink.data.eq(self.sink.data),
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tx.sink.charisk.eq(self.sink.charisk),
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self.sink.ack.eq(tx.sink.ack)
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),
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If(receive_align,
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rx.source.ack.eq(1)
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).Else(
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self.source.stb.eq(rx.source.stb),
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self.source.data.eq(rx.source.data),
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self.source.charisk.eq(rx.source.charisk),
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rx.source.ack.eq(1)
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)
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# ctrl
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).Else(
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tx.sink.stb.eq(ctrl.source.stb),
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tx.sink.data.eq(ctrl.source.data),
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tx.sink.charisk.eq(ctrl.source.charisk),
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ctrl.sink.stb.eq(rx.source.stb),
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ctrl.sink.data.eq(rx.source.data),
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rx.source.ack.eq(1),
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)
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self.demux.sel.eq(ctrl.ready),
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Record.connect(trx.source, self.rx.sink),
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Record.connect(self.rx.source, self.demux.sink),
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Record.connect(self.demux.source0, ctrl.sink),
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Record.connect(self.demux.source1, self.align_remover.sink),
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Record.connect(self.align_remover.source, self.source)
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]
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@ -6,6 +6,9 @@ CMD = PYTHONPATH=$(MSCDIR) $(PYTHON)
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CC=gcc
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CFLAGS =-Wall -O0
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phy_datapath_tb:
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$(CMD) phy_datapath_tb.py
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crc_tb:
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$(CC) $(CFLAGS) $(INC) -o crc crc.c
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$(CMD) crc_tb.py
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@ -0,0 +1,88 @@
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from lib.sata.common import *
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from lib.sata.phy.datapath import SATAPHYDatapath
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from lib.sata.test.common import *
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class DataPacket(list):
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def __init__(self, data=[]):
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self.ongoing = False
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self.done = False
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for d in data:
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self.append(d)
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class DataStreamer(PacketStreamer):
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def __init__(self):
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PacketStreamer.__init__(self, phy_description(32), DataPacket)
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def do_simulation(self, selfp):
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PacketStreamer.do_simulation(self, selfp)
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selfp.source.charisk = 0
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# Note: for simplicity we generate charisk by detecting
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# primitives in data
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for k, v in primitives.items():
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try:
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if self.source_data == v:
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selfp.source.charisk = 0b0001
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except:
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pass
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class DataLogger(PacketLogger):
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def __init__(self):
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PacketLogger.__init__(self, phy_description(32), DataPacket)
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class TRX(Module):
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def __init__(self):
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self.sink = Sink(phy_description(32))
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self.source = Source(phy_description(32))
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self.comb += Record.connect(self.sink, self.source)
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class CTRL(Module):
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def __init__(self):
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self.sink = Sink(phy_description(32))
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self.source = Source(phy_description(32))
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self.ready = Signal(reset=1)
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class TB(Module):
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def __init__(self):
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# use sys_clk for each clock_domain
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self.clock_domains.cd_sata_rx = ClockDomain()
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self.clock_domains.cd_sata_tx = ClockDomain()
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self.comb += [
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self.cd_sata_rx.clk.eq(ClockSignal()),
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self.cd_sata_rx.rst.eq(ResetSignal()),
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self.cd_sata_tx.clk.eq(ClockSignal()),
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self.cd_sata_tx.rst.eq(ResetSignal()),
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]
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self.streamer = DataStreamer()
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self.streamer_randomizer = Randomizer(phy_description(32), level=0)
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self.trx = TRX()
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self.ctrl = CTRL()
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self.datapath = SATAPHYDatapath(self.trx, self.ctrl)
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self.logger_randomizer = Randomizer(phy_description(32), level=0)
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self.logger = DataLogger()
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self.pipeline = Pipeline(
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self.streamer,
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self.streamer_randomizer,
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self.datapath,
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self.logger_randomizer,
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self.logger
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)
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def gen_simulation(self, selfp):
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streamer_packet = DataPacket([seed_to_data(i, False) for i in range(512)])
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yield from self.streamer.send(streamer_packet)
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yield from self.logger.receive(512)
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for d in self.logger.packet:
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r = "%08x " %d
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r +=decode_primitive(d)
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print(r)
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# check results
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#s, l, e = check(streamer_packet, self.logger.packet)
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#print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
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