Use new bitwidth/signedness system

constraints.py

@@ -4,7 +4,7 @@ class Constraints:
 		def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
 			self.constraints.append((signal, vec, pin, iostandard, extra))
 		def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
-			assert(signal.bv.width == len(pins))
+			assert(signal.nbits == len(pins))
 			i = 0
 			for p in pins:
 				add(signal, p, i, iostandard, extra)

milkymist/asmicon/bankmachine.py

@@ -42,8 +42,8 @@ class _Selector:
 		self.nslots = len(self.slots)
 		self.stb = Signal()
 		self.ack = Signal()
-		self.tag = Signal(BV(bits_for(self.nslots-1)))
-		self.adr = Signal(self.slots[0].adr.bv)
+		self.tag = Signal(bits_for(self.nslots-1))
+		self.adr = Signal(self.slots[0].adr.nbits)
 		self.we = Signal()
 		
 		# derived classes should drive rr.request
@@ -54,7 +54,7 @@ class _Selector:
 		rr = self.rr
 		
 		# Multiplex
-		state = Signal(BV(2))
+		state = Signal(2)
 		comb += [
 			state.eq(Array(slot.state for slot in self.slots)[rr.grant]),
 			self.adr.eq(Array(slot.adr for slot in self.slots)[rr.grant]),
@@ -98,9 +98,9 @@ class _FullSelector(_Selector):
 			outstandings.append(outstanding)
 		
 		# Row tracking
-		openrow_r = Signal(BV(self.slicer.geom_settings.row_a))
-		openrow_n = Signal(BV(self.slicer.geom_settings.row_a))
-		openrow = Signal(BV(self.slicer.geom_settings.row_a))
+		openrow_r = Signal(self.slicer.geom_settings.row_a)
+		openrow_n = Signal(self.slicer.geom_settings.row_a)
+		openrow = Signal(self.slicer.geom_settings.row_a)
 		comb += [
 			openrow_n.eq(self.slicer.row(self.adr)),
 			If(self.stb,
@@ -207,7 +207,7 @@ class BankMachine:
 		
 		# Row tracking
 		has_openrow = Signal()
-		openrow = Signal(BV(self.geom_settings.row_a))
+		openrow = Signal(self.geom_settings.row_a)
 		hit = Signal()
 		comb.append(hit.eq(openrow == slicer.row(cmdsource.adr)))
 		track_open = Signal()
@@ -238,7 +238,7 @@ class BankMachine:
 		# Respect write-to-precharge specification
 		precharge_ok = Signal()
 		t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
-		unsafe_precharge_count = Signal(BV(bits_for(t_unsafe_precharge)))
+		unsafe_precharge_count = Signal(bits_for(t_unsafe_precharge))
 		comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
 		sync += [
 			If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,

milkymist/asmicon/multiplexer.py

@@ -5,8 +5,8 @@ from migen.corelogic.fsm import FSM
 
 class CommandRequest:
 	def __init__(self, a, ba):
-		self.a = Signal(BV(a))
-		self.ba = Signal(BV(ba))
+		self.a = Signal(a)
+		self.ba = Signal(ba)
 		self.cas_n = Signal(reset=1)
 		self.ras_n = Signal(reset=1)
 		self.we_n = Signal(reset=1)
@@ -18,7 +18,7 @@ class CommandRequestRW(CommandRequest):
 		self.ack = Signal()
 		self.is_read = Signal()
 		self.is_write = Signal()
-		self.tag = Signal(BV(tagbits))
+		self.tag = Signal(tagbits)
 
 class _CommandChooser:
 	def __init__(self, requests, tagbits):
@@ -64,7 +64,7 @@ class _Steerer:
 		
 		ncmd = len(self.commands)
 		nph = len(self.dfi.phases)
-		self.sel = [Signal(BV(bits_for(ncmd-1))) for i in range(nph)]
+		self.sel = [Signal(bits_for(ncmd-1)) for i in range(nph)]
 	
 	def get_fragment(self):
 		comb = []
@@ -103,9 +103,9 @@ class _Datapath:
 		tagbits = len(self.hub.tag_call)
 		
 		rd_valid = Signal()
-		rd_tag = Signal(BV(tagbits))
+		rd_tag = Signal(tagbits)
 		wr_valid = Signal()
-		wr_tag = Signal(BV(tagbits))
+		wr_tag = Signal(tagbits)
 		comb += [
 			self.hub.call.eq(rd_valid | wr_valid),
 			If(wr_valid,
@@ -117,7 +117,7 @@ class _Datapath:
 		
 		rd_delay = self.timing_settings.rd_delay + 1
 		rd_valid_d = [Signal() for i in range(rd_delay)]
-		rd_tag_d = [Signal(BV(tagbits)) for i in range(rd_delay)]
+		rd_tag_d = [Signal(tagbits) for i in range(rd_delay)]
 		for i in range(rd_delay):
 			if i:
 				sync += [
@@ -194,7 +194,7 @@ class Multiplexer:
 			max_time = Signal()
 			if timeout:
 				t = timeout - 1
-				time = Signal(BV(bits_for(t)))
+				time = Signal(bits_for(t))
 				comb.append(max_time.eq(time == 0))
 				sync.append(
 					If(~en,

milkymist/asmicon/refresher.py

@@ -45,7 +45,7 @@ class Refresher:
 		])
 		
 		# Periodic refresh counter
-		counter = Signal(BV(bits_for(self.tREFI - 1)))
+		counter = Signal(bits_for(self.tREFI - 1))
 		start = Signal()
 		sync += [
 			start.eq(0),

milkymist/framebuffer/__init__.py

@@ -12,36 +12,36 @@ _vbits = 11
 _bpp = 32
 _bpc = 10
 _pixel_layout = [
-	("b", BV(_bpc)),
-	("g", BV(_bpc)),
-	("r", BV(_bpc)),
-	("pad", BV(_bpp-3*_bpc))
+	("b", _bpc),
+	("g", _bpc),
+	("r", _bpc),
+	("pad", _bpp-3*_bpc)
 ]
 
 _bpc_dac = 8
 _dac_layout = [
-	("hsync", BV(1)),
-	("vsync", BV(1)),
-	("b", BV(_bpc_dac)),
-	("g", BV(_bpc_dac)),
-	("r", BV(_bpc_dac))
+	("hsync", 1),
+	("vsync", 1),
+	("b", _bpc_dac),
+	("g", _bpc_dac),
+	("r", _bpc_dac)
 ]
 
 class _FrameInitiator(spi.SingleGenerator):
 	def __init__(self, asmi_bits, length_bits, alignment_bits):
 		layout = [
-			("hres", BV(_hbits), 640),
-			("hsync_start", BV(_hbits), 656),
-			("hsync_end", BV(_hbits), 752),
-			("hscan", BV(_hbits), 799),
+			("hres", _hbits, 640),
+			("hsync_start", _hbits, 656),
+			("hsync_end", _hbits, 752),
+			("hscan", _hbits, 799),
 			
-			("vres", BV(_vbits), 480),
-			("vsync_start", BV(_vbits), 492),
-			("vsync_end", BV(_vbits), 494),
-			("vscan", BV(_vbits), 524),
+			("vres", _vbits, 480),
+			("vsync_start", _vbits, 492),
+			("vsync_end", _vbits, 494),
+			("vscan", _vbits, 524),
 			
-			("base", BV(asmi_bits), 0, alignment_bits),
-			("length", BV(length_bits), 640*480*4, alignment_bits)
+			("base", asmi_bits, 0, alignment_bits),
+			("length", length_bits, 640*480*4, alignment_bits)
 		]
 		super().__init__(layout, spi.MODE_CONTINUOUS)
 
@@ -49,14 +49,14 @@ class VTG(Actor):
 	def __init__(self):
 		super().__init__(
 			("timing", Sink, [
-				("hres", BV(_hbits)),
-				("hsync_start", BV(_hbits)),
-				("hsync_end", BV(_hbits)),
-				("hscan", BV(_hbits)),
-				("vres", BV(_vbits)),
-				("vsync_start", BV(_vbits)),
-				("vsync_end", BV(_vbits)),
-				("vscan", BV(_vbits))]),
+				("hres", _hbits),
+				("hsync_start", _hbits),
+				("hsync_end", _hbits),
+				("hscan", _hbits),
+				("vres", _vbits),
+				("vsync_start", _vbits),
+				("vsync_end", _vbits),
+				("vscan", _vbits)]),
 			("pixels", Sink, _pixel_layout),
 			("dac", Source, _dac_layout)
 		)
@@ -67,8 +67,8 @@ class VTG(Actor):
 		active = Signal()
 		
 		generate_en = Signal()
-		hcounter = Signal(BV(_hbits))
-		vcounter = Signal(BV(_vbits))
+		hcounter = Signal(_hbits)
+		vcounter = Signal(_vbits)
 		
 		skip = _bpc - _bpc_dac
 		comb = [
@@ -118,9 +118,9 @@ class FIFO(Actor):
 		
 		self.vga_hsync_n = Signal()
 		self.vga_vsync_n = Signal()
-		self.vga_r = Signal(BV(_bpc_dac))
-		self.vga_g = Signal(BV(_bpc_dac))
-		self.vga_b = Signal(BV(_bpc_dac))
+		self.vga_r = Signal(_bpc_dac)
+		self.vga_g = Signal(_bpc_dac)
+		self.vga_b = Signal(_bpc_dac)
 	
 	def get_fragment(self):
 		data_width = 2+3*_bpc_dac
@@ -128,17 +128,17 @@ class FIFO(Actor):
 			Instance.Parameter("data_width", data_width),
 			Instance.Parameter("address_width", 8),
 	
-			Instance.Output("data_out", BV(data_width)),
-			Instance.Output("empty", BV(1)),
-			Instance.Input("read_en", BV(1)),
+			Instance.Output("data_out", data_width),
+			Instance.Output("empty", 1),
+			Instance.Input("read_en", 1),
 			Instance.ClockPort("clk_read", "vga"),
 
-			Instance.Input("data_in", BV(data_width)),
-			Instance.Output("full", BV(1)),
-			Instance.Input("write_en", BV(1)),
+			Instance.Input("data_in", data_width),
+			Instance.Output("full", 1),
+			Instance.Input("write_en", 1),
 			Instance.ClockPort("clk_write"),
 			
-			Instance.Input("rst", BV(1)))
+			Instance.Input("rst", 1))
 		t = self.token("dac")
 		return Fragment(
 			[

milkymist/lm32/__init__.py

@@ -5,7 +5,7 @@ class LM32:
 	def __init__(self):
 		self.ibus = i = wishbone.Interface()
 		self.dbus = d = wishbone.Interface()
-		self.interrupt = Signal(BV(32))
+		self.interrupt = Signal(32)
 		self.ext_break = Signal()
 		self._inst = Instance("lm32_top",
 			Instance.ClockPort("clk_i"),
@@ -14,33 +14,33 @@ class LM32:
 			Instance.Input("interrupt", self.interrupt),
 			#Instance.Input("ext_break", self.ext_break),
 		
-			Instance.Output("I_ADR_O", BV(32)),
+			Instance.Output("I_ADR_O", 32),
 			Instance.Output("I_DAT_O", i.dat_w),
 			Instance.Output("I_SEL_O", i.sel),
 			Instance.Output("I_CYC_O", i.cyc),
 			Instance.Output("I_STB_O", i.stb),
 			Instance.Output("I_WE_O", i.we),
 			Instance.Output("I_CTI_O", i.cti),
-			Instance.Output("I_LOCK_O", BV(1)),
+			Instance.Output("I_LOCK_O", 1),
 			Instance.Output("I_BTE_O", i.bte),
 			Instance.Input("I_DAT_I", i.dat_r),
 			Instance.Input("I_ACK_I", i.ack),
 			Instance.Input("I_ERR_I", i.err),
-			Instance.Input("I_RTY_I", BV(1)),
+			Instance.Input("I_RTY_I", 1),
 			
-			Instance.Output("D_ADR_O", BV(32)),
+			Instance.Output("D_ADR_O", 32),
 			Instance.Output("D_DAT_O", d.dat_w),
 			Instance.Output("D_SEL_O", d.sel),
 			Instance.Output("D_CYC_O", d.cyc),
 			Instance.Output("D_STB_O", d.stb),
 			Instance.Output("D_WE_O", d.we),
 			Instance.Output("D_CTI_O", d.cti),
-			Instance.Output("D_LOCK_O", BV(1)),
+			Instance.Output("D_LOCK_O", 1),
 			Instance.Output("D_BTE_O", d.bte),
 			Instance.Input("D_DAT_I", d.dat_r),
 			Instance.Input("D_ACK_I", d.ack),
 			Instance.Input("D_ERR_I", d.err),
-			Instance.Input("D_RTY_I", BV(1)))
+			Instance.Input("D_RTY_I", 1))
 
 	def get_fragment(self):
 		comb = [

milkymist/minimac3/__init__.py

@@ -10,11 +10,11 @@ class MiniMAC:
 	def __init__(self, address):
 		# PHY signals
 		self.phy_tx_clk = Signal()
-		self.phy_tx_data = Signal(BV(4))
+		self.phy_tx_data = Signal(4)
 		self.phy_tx_en = Signal()
 		self.phy_tx_er = Signal()
 		self.phy_rx_clk = Signal()
-		self.phy_rx_data = Signal(BV(4))
+		self.phy_rx_data = Signal(4)
 		self.phy_dv = Signal()
 		self.phy_rx_er = Signal()
 		self.phy_col = Signal()

milkymist/norflash/__init__.py

@@ -8,8 +8,8 @@ class NorFlash:
 		self.rd_timing = rd_timing
 		
 		self.bus = wishbone.Interface()
-		self.adr = Signal(BV(adr_width-1))
-		self.d = Signal(BV(16))
+		self.adr = Signal(adr_width-1)
+		self.d = Signal(16)
 		self.oe_n = Signal()
 		self.we_n = Signal()
 		self.ce_n = Signal()

milkymist/s6ddrphy/__init__.py

@@ -30,7 +30,7 @@ class S6DDRPHY:
 			("sd_dqs", d//16, Instance.InOut)
 			
 		]:
-			s = Signal(BV(width), name=name)
+			s = Signal(width, name=name)
 			setattr(self, name, s)
 			inst_items.append(cl(name, s))
 		

milkymist/uart/__init__.py

@@ -19,7 +19,7 @@ class UART:
 	
 	def get_fragment(self):
 		enable16 = Signal()
-		enable16_counter = Signal(BV(16))
+		enable16_counter = Signal(16)
 		comb = [
 			enable16.eq(enable16_counter == 0)
 		]
@@ -30,9 +30,9 @@ class UART:
 		]
 		
 		# TX
-		tx_reg = Signal(BV(8))
-		tx_bitcount = Signal(BV(4))
-		tx_count16 = Signal(BV(4))
+		tx_reg = Signal(8)
+		tx_bitcount = Signal(4)
+		tx_count16 = Signal(4)
 		tx_busy = self._tx_event.trigger
 		sync += [
 			If(self._rxtx.re,
@@ -66,9 +66,9 @@ class UART:
 			rx.eq(rx0)
 		]
 		rx_r = Signal()
-		rx_reg = Signal(BV(8))
-		rx_bitcount = Signal(BV(4))
-		rx_count16 = Signal(BV(4))
+		rx_reg = Signal(8)
+		rx_bitcount = Signal(4)
+		rx_count16 = Signal(4)
 		rx_busy = Signal()
 		rx_done = self._rx_event.trigger
 		rx_data = self._rxtx.w