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Merge pull request #118 from mithro/uart-sync

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uart: Enable buffering the FIFO.
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enjoy-digital 2018-10-28 08:02:22 +01:00 committed by GitHub
commit 8c0982a1d5
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litex/soc/cores/uart.py
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@ -157,7 +157,7 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
fifo = stream.AsyncFIFO([("data", 8)], depth)
return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
else:
return stream.SyncFIFO([("data", 8)], depth)
return stream.SyncFIFO([("data", 8)], depth, buffered=True)
class UART(Module, AutoCSR):