Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #118 from mithro/uart-sync 

uart: Enable buffering the FIFO.
This commit is contained in:
enjoy-digital 2018-10-28 08:02:22 +01:00 committed by GitHub
parent f916705313 ba0dd5728e
commit 8c0982a1d5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/cores/uart.py
View File

@ -157,7 +157,7 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
fifo = stream.AsyncFIFO([("data", 8)], depth) fifo = stream.AsyncFIFO([("data", 8)], depth)
return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo) return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
else: else:
return stream.SyncFIFO([("data", 8)], depth) return stream.SyncFIFO([("data", 8)], depth, buffered=True)
class UART(Module, AutoCSR): class UART(Module, AutoCSR):