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fhdl/verilog: Remove dummy_signal (no longer used).

This commit is contained in:
Florent Kermarrec 2021-10-15 15:09:41 +02:00
parent f692f50d06
commit 8c3508e7f5
2 changed files with 2 additions and 29 deletions
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1
litex/build/sim/verilator.py
View File

@ -207,7 +207,6 @@ class SimVerilatorToolchain:
# Generate verilog # Generate verilog
v_output = platform.get_verilog(fragment, v_output = platform.get_verilog(fragment,
name = build_name, name = build_name,
dummy_signal = False,
regular_comb = regular_comb, regular_comb = regular_comb,
blocking_assign = True) blocking_assign = True)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)

30
litex/gen/fhdl/verilog.py
View File

@ -374,21 +374,9 @@ def _print_module(f, ios, name, ns, attr_translate):
# COMBINATORIAL LOGIC # # COMBINATORIAL LOGIC #
# ------------------------------------------------------------------------------------------------ # # ------------------------------------------------------------------------------------------------ #
def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign): def _print_combinatorial_logic_sim(f, ns, blocking_assign):
r = "" r = ""
if f.comb: if f.comb:
if dummy_signal:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate_off\n"
syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _print_signal(ns, dummy_s) + ";\n"
r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
r += syn_on
from collections import defaultdict from collections import defaultdict
target_stmt_map = defaultdict(list) target_stmt_map = defaultdict(list)
@ -405,12 +393,6 @@ def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign):
if len(stmts) == 1 and isinstance(stmts[0], _Assign): if len(stmts) == 1 and isinstance(stmts[0], _Assign):
r += "assign " + _print_node(ns, _AT_BLOCKING, 0, stmts[0]) r += "assign " + _print_node(ns, _AT_BLOCKING, 0, stmts[0])
else: else:
if dummy_signal:
dummy_d = Signal(name_override="dummy_d")
r += "\n" + syn_off
r += "reg " + _print_signal(ns, dummy_d) + ";\n"
r += syn_on
r += "always @(*) begin\n" r += "always @(*) begin\n"
if blocking_assign: if blocking_assign:
r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n" r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n"
@ -418,10 +400,6 @@ def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign):
else: else:
r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n" r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
r += _print_node(ns, _AT_NONBLOCKING, 1, stmts, t) r += _print_node(ns, _AT_NONBLOCKING, 1, stmts, t)
if dummy_signal:
r += syn_off
r += "\t" + ns.get_name(dummy_d) + " = " + ns.get_name(dummy_s) + ";\n"
r += syn_on
r += "end\n" r += "end\n"
r += "\n" r += "\n"
return r return r
@ -493,7 +471,6 @@ def convert(f, ios=set(), name="top",
special_overrides = dict(), special_overrides = dict(),
attr_translate = DummyAttrTranslate(), attr_translate = DummyAttrTranslate(),
create_clock_domains = True, create_clock_domains = True,
dummy_signal = True,
blocking_assign = False, blocking_assign = False,
regular_comb = True): regular_comb = True):
@ -568,10 +545,7 @@ def convert(f, ios=set(), name="top",
blocking_assign = blocking_assign blocking_assign = blocking_assign
) )
else: else:
verilog += _print_combinatorial_logic_sim(f, ns, verilog += _print_combinatorial_logic_sim(f, ns, blocking_assign=blocking_assign)
dummy_signal = dummy_signal,
blocking_assign = blocking_assign
)
# Synchronous Logic. # Synchronous Logic.
verilog += _print_synchronous_logic(f, ns) verilog += _print_synchronous_logic(f, ns)