add input pipe stage option

This commit is contained in:
Florent Kermarrec 2014-10-28 20:53:26 +01:00
parent d860813dec
commit 8c5c32751e
1 changed files with 19 additions and 5 deletions

View File

@ -18,10 +18,11 @@ def _getattr_all(l, attr):
return r return r
class MiLa(Module, AutoCSR): class MiLa(Module, AutoCSR):
def __init__(self, depth, dat, with_rle=False, clk_domain="sys"): def __init__(self, depth, dat, with_rle=False, clk_domain="sys", pipe=False):
self.depth = depth self.depth = depth
self.with_rle = with_rle self.with_rle = with_rle
self.clk_domain = clk_domain self.clk_domain = clk_domain
self.pipe = pipe
self.ports = [] self.ports = []
self.width = flen(dat) self.width = flen(dat)
@ -33,12 +34,25 @@ class MiLa(Module, AutoCSR):
self.ports.append(port) self.ports.append(port)
def do_finalize(self): def do_finalize(self):
stb = self.stb
dat = self.dat
if self.pipe:
sync = getattr(self.sync, self.clk_domain)
stb_new = Signal()
dat_new = Signal(flen(dat))
sync += [
stb_new.eq(stb),
dat_new.eq(dat)
]
stb = stb_new
dat = dat_new
if self.clk_domain is not "sys": if self.clk_domain is not "sys":
fifo = AsyncFIFO([("dat", self.width)], 32) fifo = AsyncFIFO([("dat", self.width)], 32)
self.submodules += RenameClockDomains(fifo, {"write": self.clk_domain, "read": "sys"}) self.submodules += RenameClockDomains(fifo, {"write": self.clk_domain, "read": "sys"})
self.comb += [ self.comb += [
fifo.sink.stb.eq(self.stb), fifo.sink.stb.eq(stb),
fifo.sink.dat.eq(self.dat) fifo.sink.dat.eq(dat)
] ]
sink = Record(dat_layout(self.width)) sink = Record(dat_layout(self.width))
self.comb += [ self.comb += [
@ -49,8 +63,8 @@ class MiLa(Module, AutoCSR):
else: else:
sink = Record(dat_layout(self.width)) sink = Record(dat_layout(self.width))
self.comb += [ self.comb += [
sink.stb.eq(self.stb), sink.stb.eq(stb),
sink.dat.eq(self.dat) sink.dat.eq(dat)
] ]
self.submodules.trigger = trigger = Trigger(self.width, self.ports) self.submodules.trigger = trigger = Trigger(self.width, self.ports)