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boards/platforms: add separators, cleanup imports

This commit is contained in:
Florent Kermarrec 2019-04-21 00:44:23 +02:00
parent cb8c26d1b8
commit 8c78997089
14 changed files with 62 additions and 13 deletions
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10
litex/boards/platforms/arty.py
View File

@ -5,7 +5,9 @@
# License: BSD # License: BSD
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
@ -58,7 +60,8 @@ _io = [
("serial", 0, ("serial", 0,
Subsignal("tx", Pins("D10")), Subsignal("tx", Pins("D10")),
Subsignal("rx", Pins("A9")), Subsignal("rx", Pins("A9")),
IOStandard("LVCMOS33")), IOStandard("LVCMOS33")
),
("spi", 0, ("spi", 0,
Subsignal("clk", Pins("F1")), Subsignal("clk", Pins("F1")),
@ -137,6 +140,8 @@ _io = [
), ),
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("pmoda", "G13 B11 A11 D12 D13 B18 A18 K16"), ("pmoda", "G13 B11 A11 D12 D13 B18 A18 K16"),
("pmodb", "E15 E16 D15 C15 J17 J18 K15 J15"), ("pmodb", "E15 E16 D15 C15 J17 J18 K15 J15"),
@ -228,6 +233,7 @@ _connectors = [
} ), } ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk100" default_clk_name = "clk100"

4
litex/boards/platforms/avalanche.py
View File

@ -4,6 +4,8 @@
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.microsemi import MicrosemiPlatform from litex.build.microsemi import MicrosemiPlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("clk50", 0, Pins("R1"), IOStandard("LVCMOS25")), ("clk50", 0, Pins("R1"), IOStandard("LVCMOS25")),
("clk50", 1, Pins("J3"), IOStandard("LVCMOS25")), ("clk50", 1, Pins("J3"), IOStandard("LVCMOS25")),
@ -82,6 +84,8 @@ _io = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(MicrosemiPlatform): class Platform(MicrosemiPlatform):
default_clk_name = "clk50" default_clk_name = "clk50"
default_clk_period = 20.0 default_clk_period = 20.0

2
litex/boards/platforms/de0nano.py
View File

@ -5,6 +5,7 @@ from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")), ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),
@ -91,6 +92,7 @@ _io = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform): class Platform(AlteraPlatform):
default_clk_name = "clk50" default_clk_name = "clk50"

4
litex/boards/platforms/genesys2.py
View File

@ -1,6 +1,7 @@
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("user_led", 0, Pins("T28"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("T28"), IOStandard("LVCMOS33")),
@ -88,6 +89,7 @@ _io = [
), ),
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("HPC", { ("HPC", {
@ -101,6 +103,8 @@ _connectors = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk200" default_clk_name = "clk200"
default_clk_period = 5 default_clk_period = 5

9
litex/boards/platforms/kc705.py
View File

@ -1,7 +1,7 @@
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.xilinx.ise import XilinxISEToolchain
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
@ -58,7 +58,8 @@ _io = [
Subsignal("rts", Pins("K23")), Subsignal("rts", Pins("K23")),
Subsignal("tx", Pins("K24")), Subsignal("tx", Pins("K24")),
Subsignal("rx", Pins("M19")), Subsignal("rx", Pins("M19")),
IOStandard("LVCMOS25")), IOStandard("LVCMOS25")
),
("spiflash", 0, # clock needs to be accessed through STARTUPE2 ("spiflash", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("U19")), Subsignal("cs_n", Pins("U19")),
@ -284,6 +285,7 @@ _io = [
), ),
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("HPC", { ("HPC", {
@ -521,6 +523,7 @@ _connectors = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk156" default_clk_name = "clk156"

4
litex/boards/platforms/kcu105.py
View File

@ -1,6 +1,7 @@
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")), ("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")),
@ -235,6 +236,8 @@ _io = [
("sfp_tx_disable_n", 1, Pins("D28"), IOStandard("LVCMOS18")), ("sfp_tx_disable_n", 1, Pins("D28"), IOStandard("LVCMOS18")),
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("HPC", { ("HPC", {
"DP0_C2M_P": "F6", "DP0_C2M_P": "F6",
@ -476,6 +479,7 @@ _connectors = [
) )
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk125" default_clk_name = "clk125"

2
litex/boards/platforms/machxo3.py
View File

@ -5,6 +5,7 @@ from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer from litex.build.lattice.programmer import LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("clk12", 0, Pins("C8"), IOStandard("LVCMOS33")), ("clk12", 0, Pins("C8"), IOStandard("LVCMOS33")),
@ -30,6 +31,7 @@ _io = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform): class Platform(LatticePlatform):
default_clk_name = "clk12" default_clk_name = "clk12"

6
litex/boards/platforms/minispartan6.py
View File

@ -3,8 +3,9 @@
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform from litex.build.xilinx import XilinxPlatform
from litex.build.xilinx.programmer import XC3SProg, FpgaProg from litex.build.xilinx.programmer import FpgaProg
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")),
@ -99,6 +100,8 @@ _io = [
) )
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"), ("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"),
("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"), ("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"),
@ -108,6 +111,7 @@ _connectors = [
("F", "E2 E1 E4 F4 F5 G3 F3 G1 H3 H1 H2 J1") ("F", "E2 E1 E4 F4 F5 G3 F3 G1 H3 H1 H2 J1")
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk32" default_clk_name = "clk32"

5
litex/boards/platforms/nexys4ddr.py
View File

@ -2,7 +2,9 @@
# License: BSD # License: BSD
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
@ -81,6 +83,7 @@ _io = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk100" default_clk_name = "clk100"

8
litex/boards/platforms/nexys_video.py
View File

@ -2,7 +2,9 @@
# License: BSD # License: BSD
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")), ("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")),
@ -127,6 +129,8 @@ _io = [
), ),
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("LPC", { ("LPC", {
"DP0_C2M_P": "D7", "DP0_C2M_P": "D7",
@ -211,6 +215,8 @@ _connectors = [
) )
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk100" default_clk_name = "clk100"
default_clk_period = 10.0 default_clk_period = 10.0

6
litex/boards/platforms/tinyfpga_bx.py
View File

@ -2,6 +2,8 @@ from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import TinyProgProgrammer from litex.build.lattice.programmer import TinyProgProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("user_led", 0, Pins("B3"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("B3"), IOStandard("LVCMOS33")),
@ -30,6 +32,8 @@ _io = [
("clk16", 0, Pins("B2"), IOStandard("LVCMOS33")) ("clk16", 0, Pins("B2"), IOStandard("LVCMOS33"))
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
# A2-H2, Pins 1-13 # A2-H2, Pins 1-13
# H9-A6, Pins 14-24 # H9-A6, Pins 14-24
@ -38,7 +42,6 @@ _connectors = [
("EXTRA", "G1 J3 J4 G9 J9 E8 J2") ("EXTRA", "G1 J3 J4 G9 J9 E8 J2")
] ]
# Default peripherals # Default peripherals
serial = [ serial = [
("serial", 0, ("serial", 0,
@ -48,6 +51,7 @@ serial = [
) )
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform): class Platform(LatticePlatform):
default_clk_name = "clk16" default_clk_name = "clk16"

2
litex/boards/platforms/ulx3s.py
View File

@ -4,6 +4,7 @@
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")), ("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")),
@ -64,6 +65,7 @@ _io = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform): class Platform(LatticePlatform):
default_clk_name = "clk100" default_clk_name = "clk100"

2
litex/boards/platforms/versa_ecp3.py
View File

@ -5,6 +5,7 @@ from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer from litex.build.lattice.programmer import LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("clk100", 0, Pins("L5"), IOStandard("LVDS25")), ("clk100", 0, Pins("L5"), IOStandard("LVDS25")),
@ -74,6 +75,7 @@ _io = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform): class Platform(LatticePlatform):
default_clk_name = "clk100" default_clk_name = "clk100"

3
litex/boards/platforms/versa_ecp5.py
View File

@ -5,6 +5,7 @@ from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer from litex.build.lattice.programmer import LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("clk100", 0, Pins("P3"), IOStandard("LVDS")), ("clk100", 0, Pins("P3"), IOStandard("LVDS")),
@ -127,6 +128,7 @@ _ecp5_soc_hat_io = [
), ),
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("X3", ("X3",
@ -174,6 +176,7 @@ _connectors = [
), ),
] ]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform): class Platform(LatticePlatform):
default_clk_name = "clk100" default_clk_name = "clk100"