cpu/rocket/core: Initial changes for .dts generation through json2dts.
For now just add information missing by json2dts to generate the .dts similarly to VexRiscv-SMP.
This commit is contained in:
Florent Kermarrec
parent
c6394c8f27
commit
8c79c2599f
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@ -43,62 +43,62 @@ class Open(Signal): pass
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = {
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"standard": "freechips.rocketchip.system.LitexConfig",
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"linux": "freechips.rocketchip.system.LitexLinuxConfig",
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"linux4": "freechips.rocketchip.system.LitexLinux4Config",
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"linuxd": "freechips.rocketchip.system.LitexLinuxDConfig",
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"linux2d": "freechips.rocketchip.system.LitexLinux2DConfig",
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"linuxq": "freechips.rocketchip.system.LitexLinuxQConfig",
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"linux2q": "freechips.rocketchip.system.LitexLinux2QConfig",
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"full": "freechips.rocketchip.system.LitexFullConfig",
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"fulld": "freechips.rocketchip.system.LitexFullDConfig",
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"full4d": "freechips.rocketchip.system.LitexFull4DConfig",
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"fullq": "freechips.rocketchip.system.LitexFullQConfig",
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"full4q": "freechips.rocketchip.system.LitexFull4QConfig",
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"fullo": "freechips.rocketchip.system.LitexFullOConfig",
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"full4o": "freechips.rocketchip.system.LitexFull4OConfig",
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"full8o": "freechips.rocketchip.system.LitexFull8OConfig",
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"standard" : "freechips.rocketchip.system.LitexConfig",
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"linux" : "freechips.rocketchip.system.LitexLinuxConfig",
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"linux4" : "freechips.rocketchip.system.LitexLinux4Config",
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"linuxd" : "freechips.rocketchip.system.LitexLinuxDConfig",
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"linux2d" : "freechips.rocketchip.system.LitexLinux2DConfig",
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"linuxq" : "freechips.rocketchip.system.LitexLinuxQConfig",
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"linux2q" : "freechips.rocketchip.system.LitexLinux2QConfig",
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"full" : "freechips.rocketchip.system.LitexFullConfig",
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"fulld" : "freechips.rocketchip.system.LitexFullDConfig",
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"full4d" : "freechips.rocketchip.system.LitexFull4DConfig",
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"fullq" : "freechips.rocketchip.system.LitexFullQConfig",
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"full4q" : "freechips.rocketchip.system.LitexFull4QConfig",
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"fullo" : "freechips.rocketchip.system.LitexFullOConfig",
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"full4o" : "freechips.rocketchip.system.LitexFull4OConfig",
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"full8o" : "freechips.rocketchip.system.LitexFull8OConfig",
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}
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# GCC Flags-----------------------------------------------------------------------------------------
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GCC_FLAGS = {
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"standard": "-march=rv64imac -mabi=lp64 ",
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"linux": "-march=rv64imac -mabi=lp64 ",
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"linux4": "-march=rv64imac -mabi=lp64 ",
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"linuxd": "-march=rv64imac -mabi=lp64 ",
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"linux2d": "-march=rv64imac -mabi=lp64 ",
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"linuxq": "-march=rv64imac -mabi=lp64 ",
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"linux2q": "-march=rv64imac -mabi=lp64 ",
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"full": "-march=rv64imafdc -mabi=lp64 ",
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"fulld": "-march=rv64imafdc -mabi=lp64 ",
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"full4d": "-march=rv64imafdc -mabi=lp64 ",
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"fullq": "-march=rv64imafdc -mabi=lp64 ",
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"full4q": "-march=rv64imafdc -mabi=lp64 ",
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"fullo": "-march=rv64imafdc -mabi=lp64 ",
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"full4o": "-march=rv64imafdc -mabi=lp64 ",
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"full8o": "-march=rv64imafdc -mabi=lp64 ",
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"standard" : "-march=rv64imac -mabi=lp64 ",
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"linux" : "-march=rv64imac -mabi=lp64 ",
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"linux4" : "-march=rv64imac -mabi=lp64 ",
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"linuxd" : "-march=rv64imac -mabi=lp64 ",
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"linux2d" : "-march=rv64imac -mabi=lp64 ",
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"linuxq" : "-march=rv64imac -mabi=lp64 ",
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"linux2q" : "-march=rv64imac -mabi=lp64 ",
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"full" : "-march=rv64imafdc -mabi=lp64 ",
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"fulld" : "-march=rv64imafdc -mabi=lp64 ",
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"full4d" : "-march=rv64imafdc -mabi=lp64 ",
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"fullq" : "-march=rv64imafdc -mabi=lp64 ",
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"full4q" : "-march=rv64imafdc -mabi=lp64 ",
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"fullo" : "-march=rv64imafdc -mabi=lp64 ",
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"full4o" : "-march=rv64imafdc -mabi=lp64 ",
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"full8o" : "-march=rv64imafdc -mabi=lp64 ",
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}
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# CPU Size Params ----------------------------------------------------------------------------------
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# CPU Params ----------------------------------------------------------------------------------
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CPU_SIZE_PARAMS = {
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# Variant : (mem_dw, mmio_dw, num_cores)
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"standard": ( 64, 64, 1),
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"linux": ( 64, 64, 1),
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"linux4": ( 64, 64, 4),
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"linuxd": ( 128, 64, 1),
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"linux2d": ( 128, 64, 2),
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"linuxq": ( 256, 64, 1),
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"linux2q": ( 256, 64, 2),
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"full": ( 64, 64, 1),
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"fulld": ( 128, 64, 1),
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"full4d": ( 128, 64, 4),
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"fullq": ( 256, 64, 1),
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"full4q": ( 256, 64, 4),
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"fullo": ( 512, 64, 1),
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"full4o": ( 512, 64, 4),
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"full8o": ( 512, 64, 8),
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CPU_PARAMS = {
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# Variant : (mem_dw, mmio_dw, num_cores)
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"standard" : ( 64, 64, 1),
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"linux" : ( 64, 64, 1),
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"linux4" : ( 64, 64, 4),
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"linuxd" : ( 128, 64, 1),
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"linux2d" : ( 128, 64, 2),
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"linuxq" : ( 256, 64, 1),
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"linux2q" : ( 256, 64, 2),
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"full" : ( 64, 64, 1),
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"fulld" : ( 128, 64, 1),
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"full4d" : ( 128, 64, 4),
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"fullq" : ( 256, 64, 1),
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"full4q" : ( 256, 64, 4),
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"fullo" : ( 512, 64, 1),
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"full4o" : ( 512, 64, 4),
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"full8o" : ( 512, 64, 8),
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}
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# Rocket ------------------------------------------------------------------------------------------
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@ -116,6 +116,14 @@ class Rocket(CPU):
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nop = "nop"
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io_regions = {0x1200_0000: 0x7000_0000} # Origin, Length.
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# Arch.
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@staticmethod
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def get_arch(variant):
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arch = "rv64imac"
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if "full" in variant:
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arch += "fdc"
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return arch
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# Memory Mapping.
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@property
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def mem_map(self):
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@ -124,6 +132,8 @@ class Rocket(CPU):
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"rom" : 0x1000_0000,
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"sram" : 0x1100_0000,
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"csr" : 0x1200_0000,
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"clint" : 0x1300_0000, # FIXME: Just here for .dts generation through json2ds.
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"plic" : 0x1400_0000, # FIXME: Just here for .dts generation through json2ds.
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"ethmac" : 0x3000_0000,
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"main_ram" : 0x8000_0000,
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}
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@ -132,7 +142,7 @@ class Rocket(CPU):
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@property
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def gcc_flags(self):
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flags = "-mno-save-restore "
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flags += GCC_FLAGS[self.variant]
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flags += f"-march={self.get_arch(self.variant)} -mabi=lp64 "
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flags += "-D__rocket__ "
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flags += "-mcmodel=medany"
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return flags
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@ -144,7 +154,7 @@ class Rocket(CPU):
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self.reset = Signal()
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self.interrupt = Signal(8)
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mem_dw, mmio_dw, num_cores = CPU_SIZE_PARAMS[self.variant]
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mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
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self.mem_axi = mem_axi = axi.AXIInterface(data_width=mem_dw, address_width=32, id_width=4)
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self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4)
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@ -346,6 +356,19 @@ class Rocket(CPU):
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"EICG_wrapper.v",
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)
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def add_soc_components(self, soc, soc_region_cls):
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# Get CPU Params.
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mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
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# Add OpenSBI/PLIC/CLINT regions. # FIXME: Just here for .dts generation through json2ds.
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soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="linker")
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soc.add_memory_region("plic", soc.mem_map.get("plic") , 0x40_0000, type="linker")
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soc.add_memory_region("clint", soc.mem_map.get("clint") , 0x1_0000, type="linker")
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# Define number of CPUs
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soc.add_config("CPU_COUNT", num_cores)
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soc.add_constant("CPU_ISA", self.get_arch(self.variant))
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("ExampleRocketSystem", **self.cpu_params)
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