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cpu/rocket/core: Initial changes for .dts generation through json2dts. 

For now just add information missing by json2dts to generate the .dts similarly to VexRiscv-SMP.
This commit is contained in:
Florent Kermarrec 2023-02-20 10:13:16 +01:00
parent c6394c8f27
commit 8c79c2599f
1 changed files with 73 additions and 50 deletions
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31
litex/soc/cores/cpu/rocket/core.py
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@ -80,9 +80,9 @@ GCC_FLAGS = {
"full8o" : "-march=rv64imafdc -mabi=lp64 ", "full8o" : "-march=rv64imafdc -mabi=lp64 ",
} }
# CPU Size Params ---------------------------------------------------------------------------------- # CPU Params ----------------------------------------------------------------------------------
CPU_SIZE_PARAMS = { CPU_PARAMS = {
# Variant : (mem_dw, mmio_dw, num_cores) # Variant : (mem_dw, mmio_dw, num_cores)
"standard" : ( 64, 64, 1), "standard" : ( 64, 64, 1),
"linux" : ( 64, 64, 1), "linux" : ( 64, 64, 1),
@ -116,6 +116,14 @@ class Rocket(CPU):
nop = "nop" nop = "nop"
io_regions = {0x1200_0000: 0x7000_0000} # Origin, Length. io_regions = {0x1200_0000: 0x7000_0000} # Origin, Length.
# Arch.
@staticmethod
def get_arch(variant):
arch = "rv64imac"
if "full" in variant:
arch += "fdc"
return arch
# Memory Mapping. # Memory Mapping.
@property @property
def mem_map(self): def mem_map(self):
@ -124,6 +132,8 @@ class Rocket(CPU):
"rom" : 0x1000_0000, "rom" : 0x1000_0000,
"sram" : 0x1100_0000, "sram" : 0x1100_0000,
"csr" : 0x1200_0000, "csr" : 0x1200_0000,
"clint" : 0x1300_0000, # FIXME: Just here for .dts generation through json2ds.
"plic" : 0x1400_0000, # FIXME: Just here for .dts generation through json2ds.
"ethmac" : 0x3000_0000, "ethmac" : 0x3000_0000,
"main_ram" : 0x8000_0000, "main_ram" : 0x8000_0000,
} }
@ -132,7 +142,7 @@ class Rocket(CPU):
@property @property
def gcc_flags(self): def gcc_flags(self):
flags = "-mno-save-restore " flags = "-mno-save-restore "
flags += GCC_FLAGS[self.variant] flags += f"-march={self.get_arch(self.variant)} -mabi=lp64 "
flags += "-D__rocket__ " flags += "-D__rocket__ "
flags += "-mcmodel=medany" flags += "-mcmodel=medany"
return flags return flags
@ -144,7 +154,7 @@ class Rocket(CPU):
self.reset = Signal() self.reset = Signal()
self.interrupt = Signal(8) self.interrupt = Signal(8)
mem_dw, mmio_dw, num_cores = CPU_SIZE_PARAMS[self.variant] mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
self.mem_axi = mem_axi = axi.AXIInterface(data_width=mem_dw, address_width=32, id_width=4) self.mem_axi = mem_axi = axi.AXIInterface(data_width=mem_dw, address_width=32, id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4) self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4)
@ -346,6 +356,19 @@ class Rocket(CPU):
"EICG_wrapper.v", "EICG_wrapper.v",
) )
def add_soc_components(self, soc, soc_region_cls):
# Get CPU Params.
mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
# Add OpenSBI/PLIC/CLINT regions. # FIXME: Just here for .dts generation through json2ds.
soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="linker")
soc.add_memory_region("plic", soc.mem_map.get("plic") , 0x40_0000, type="linker")
soc.add_memory_region("clint", soc.mem_map.get("clint") , 0x1_0000, type="linker")
# Define number of CPUs
soc.add_config("CPU_COUNT", num_cores)
soc.add_constant("CPU_ISA", self.get_arch(self.variant))
def do_finalize(self): def do_finalize(self):
assert hasattr(self, "reset_address") assert hasattr(self, "reset_address")
self.specials += Instance("ExampleRocketSystem", **self.cpu_params) self.specials += Instance("ExampleRocketSystem", **self.cpu_params)