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soc_sdram: change l2_size checks order

This commit is contained in:
Florent Kermarrec 2019-09-23 10:15:27 +02:00
parent a9acab99b3
commit 8c979565a8
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc_sdram.py
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@ -82,8 +82,8 @@ class SoCSDRAM(SoCCore):
geom_settings.colbits)*phy.settings.databits//8 geom_settings.colbits)*phy.settings.databits//8
main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
l2_size = 2**int(log2(self.l2_size)) # Round to nearest power of 2 l2_size = max(self.l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower
l2_size = max(l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower l2_size = 2**int(log2(l2_size)) # Round to nearest power of 2
# SoC <--> L2 Cache Wishbone interface ----------------------------------------------------- # SoC <--> L2 Cache Wishbone interface -----------------------------------------------------
wb_sdram = wishbone.Interface() wb_sdram = wishbone.Interface()