cores/jtag: cleanup instances.
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@ -22,20 +22,23 @@ class JTAGAtlantic(Module):
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self.specials += Instance("alt_jtag_atlantic",
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# Parameters
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p_LOG2_RXFIFO_DEPTH="5", # FIXME: expose?
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p_LOG2_TXFIFO_DEPTH="5", # FIXME: expose?
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p_SLD_AUTO_INSTANCE_INDEX="YES",
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p_LOG2_RXFIFO_DEPTH = "5", # FIXME: expose?
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p_LOG2_TXFIFO_DEPTH = "5", # FIXME: expose?
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p_SLD_AUTO_INSTANCE_INDEX = "YES",
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# Clk/Rst
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i_clk=ClockSignal("sys"),
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i_rst_n=~ResetSignal("sys"),
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i_clk = ClockSignal("sys"),
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i_rst_n = ~ResetSignal("sys"),
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# TX
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i_r_dat=sink.data,
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i_r_val=sink.valid,
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o_r_ena=sink.ready,
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i_r_dat = sink.data,
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i_r_val = sink.valid,
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o_r_ena = sink.ready,
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# RX
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o_t_dat=source.data,
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i_t_dav=source.ready,
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o_t_ena=source.valid,
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o_t_dat = source.data,
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i_t_dav = source.ready,
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o_t_ena = source.valid,
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)
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# Xilinx JTAG --------------------------------------------------------------------------------------
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@ -54,20 +57,19 @@ class XilinxJTAG(Module):
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# # #
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self.specials += \
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Instance(primitive,
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p_JTAG_CHAIN=chain,
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self.specials += Instance(primitive,
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p_JTAG_CHAIN = chain,
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o_RESET=self.reset,
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o_CAPTURE=self.capture,
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o_SHIFT=self.shift,
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o_UPDATE=self.update,
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o_RESET = self.reset,
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o_CAPTURE = self.capture,
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o_SHIFT = self.shift,
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o_UPDATE = self.update,
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o_TCK=self.tck,
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o_TMS=self.tms,
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o_TDI=self.tdi,
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i_TDO=self.tdo,
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)
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o_TCK = self.tck,
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o_TMS = self.tms,
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o_TDI = self.tdi,
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i_TDO = self.tdo,
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)
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class S6JTAG(XilinxJTAG):
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def __init__(self, *args, **kwargs):
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