fhdl.size: rename to bitcontainer

doc/api.rst

@@ -8,10 +8,10 @@ migen API Documentation
         :members:
         :show-inheritance:
 
-:mod:`fhdl.size` Module
+:mod:`fhdl.bitcontainer` Module
 ------------------------------
 
-.. automodule:: migen.fhdl.size
+.. automodule:: migen.fhdl.bitcontainer
         :members:
         :show-inheritance:
 

migen/fhdl/specials.py

@@ -1,7 +1,7 @@
 from operator import itemgetter
 
 from migen.fhdl.structure import *
-from migen.fhdl.size import bits_for, value_bits_sign
+from migen.fhdl.bitcontainer import bits_for, value_bits_sign
 from migen.fhdl.tools import *
 from migen.fhdl.tracer import get_obj_var_name
 from migen.fhdl.verilog import _printexpr as verilog_printexpr

migen/fhdl/std.py

@@ -1,5 +1,5 @@
 from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import TSTriple, Instance, Memory
-from migen.fhdl.size import log2_int, bits_for, flen, fiter, fslice, freversed
+from migen.fhdl.bitcontainer import log2_int, bits_for, flen, fiter, fslice, freversed
 from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains

migen/fhdl/structure.py

@@ -79,7 +79,7 @@ class Value(HUID):
 	
 	
 	def __getitem__(self, key):
-		from migen.fhdl.size import flen
+		from migen.fhdl.bitcontainer import flen
 
 		if isinstance(key, int):
 			if key < 0:
@@ -242,7 +242,7 @@ class Signal(Value):
 	related : Signal or None
 	"""
 	def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None):
-		from migen.fhdl.size import bits_for
+		from migen.fhdl.bitcontainer import bits_for
 
 		Value.__init__(self)
 		

migen/fhdl/tools.py

@@ -1,7 +1,7 @@
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Slice, _Assign
 from migen.fhdl.visit import NodeVisitor, NodeTransformer
-from migen.fhdl.size import value_bits_sign
+from migen.fhdl.bitcontainer import value_bits_sign
 from migen.util.misc import flat_iteration
 
 class _SignalLister(NodeVisitor):

migen/fhdl/verilog.py

@@ -4,7 +4,7 @@ from operator import itemgetter
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
 from migen.fhdl.tools import *
-from migen.fhdl.size import bits_for, flen
+from migen.fhdl.bitcontainer import bits_for, flen
 from migen.fhdl.namer import Namespace, build_namespace
 
 def _printsig(ns, s):

migen/genlib/cdc.py

@@ -1,5 +1,5 @@
 from migen.fhdl.std import *
-from migen.fhdl.size import value_bits_sign
+from migen.fhdl.bitcontainer import value_bits_sign
 from migen.fhdl.specials import Special
 from migen.fhdl.tools import list_signals