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ddrphy: working on hardware, simulation a bit messed up

This commit is contained in:
Sebastien Bourdeauducq 2012-02-24 15:44:51 +01:00
parent baba267db6
commit 8d4a42887e
3 changed files with 31 additions and 22 deletions
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2
software/bios/ddrinit.c
View File

@ -61,7 +61,6 @@ static void init_sequence(void)
/* Load Mode Register */
setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
//setaddr(0x0162); /* Reset DLL, CL=2.5, BL=4 */
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
cdelay(200);
@ -78,7 +77,6 @@ static void init_sequence(void)
/* Load Mode Register */
setaddr(0x0032); /* CL=3, BL=4 */
//setaddr(0x0062); /* CL=2.5, BL=4 */
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
cdelay(200);
}

6
tb/s6ddrphy/tb_s6ddrphy.v
View File

@ -123,14 +123,13 @@ initial begin
`ifdef TEST_WRITE
#13;
dfi_address_p1 <= 13'h0dbe;
#12;
dfi_address_p1 <= 0;
dfi_wrdata_en_p1 <= 1;
dfi_wrdata_mask_p0 <= 8'h12;
dfi_wrdata_mask_p1 <= 8'h34;
dfi_wrdata_p0 <= 64'hcafebabeabadface;
dfi_wrdata_p1 <= 64'h0123456789abcdef;
#12;
dfi_address_p1 <= 0;
dfi_wrdata_en_p1 <= 0;
dfi_wrdata_mask_p0 <= 0;
dfi_wrdata_mask_p1 <= 0;
@ -142,10 +141,9 @@ initial begin
`ifdef TEST_READ
#13;
dfi_address_p0 <= 13'h1234;
#12;
dfi_address_p0 <= 0;
dfi_rddata_en_p0 <= 1;
#12;
dfi_address_p0 <= 0;
dfi_rddata_en_p0 <= 0;
#15.5;
dq_tb <= 32'h12345678;

45
verilog/s6ddrphy/s6ddrphy.v
View File

@ -218,7 +218,19 @@ endgenerate
always @(posedge clk2x_270)
postamble <= drive_dqs;
reg [NUM_D-1:0] d_dfi_wrdata_p0;
reg [NUM_D-1:0] d_dfi_wrdata_p1;
reg [NUM_D/8-1:0] d_dfi_wrdata_mask_p0;
reg [NUM_D/8-1:0] d_dfi_wrdata_mask_p1;
always @(posedge sys_clk) begin
d_dfi_wrdata_p0 <= dfi_wrdata_p0;
d_dfi_wrdata_p1 <= dfi_wrdata_p1;
d_dfi_wrdata_mask_p0 <= dfi_wrdata_mask_p0;
d_dfi_wrdata_mask_p1 <= dfi_wrdata_mask_p1;
end
wire drive_dq;
wire d_drive_dq;
wire [NUM_D/2-1:0] dq_i;
wire [NUM_D/2-1:0] dq_o;
wire [NUM_D/2-1:0] dq_t;
@ -239,14 +251,14 @@ generate
.IOCE(clk4x_wr_strb),
.RST(1'b0),
.CLKDIV(sys_clk),
.D1(dfi_wrdata_p0[i+NUM_D/2]),
.D2(dfi_wrdata_p0[i]),
.D3(dfi_wrdata_p1[i+NUM_D/2]),
.D4(dfi_wrdata_p1[i]),
.D1(d_dfi_wrdata_p0[i]),
.D2(d_dfi_wrdata_p1[i+NUM_D/2]),
.D3(d_dfi_wrdata_p1[i]),
.D4(dfi_wrdata_p0[i+NUM_D/2]),
.TQ(dq_t[i]),
.T1(~drive_dq),
.T2(~drive_dq),
.T3(~drive_dq),
.T1(~d_drive_dq),
.T2(~d_drive_dq),
.T3(~d_drive_dq),
.T4(~drive_dq),
.TRAIN(1'b0),
.TCE(1'b1),
@ -313,10 +325,10 @@ generate
.IOCE(clk4x_wr_strb),
.RST(1'b0),
.CLKDIV(sys_clk),
.D1(dfi_wrdata_mask_p0[i+NUM_D/16]),
.D2(dfi_wrdata_mask_p0[i]),
.D3(dfi_wrdata_mask_p1[i+NUM_D/16]),
.D4(dfi_wrdata_mask_p1[i]),
.D1(d_dfi_wrdata_mask_p0[i]),
.D2(d_dfi_wrdata_mask_p1[i+NUM_D/16]),
.D3(d_dfi_wrdata_mask_p1[i]),
.D4(dfi_wrdata_mask_p0[i+NUM_D/16]),
.TQ(),
.T1(),
.T2(),
@ -344,16 +356,17 @@ reg d_dfi_wrdata_en_p1;
always @(posedge sys_clk)
d_dfi_wrdata_en_p1 <= dfi_wrdata_en_p1;
assign drive_dq = dfi_wrdata_en_p1;
assign d_drive_dq = d_dfi_wrdata_en_p1;
reg r_dfi_wrdata_en;
always @(posedge clk2x_270)
r_dfi_wrdata_en <= d_dfi_wrdata_en_p1;
reg r2_dfi_wrdata_en;
always @(posedge clk2x_270)
always @(posedge clk2x_270) begin
r_dfi_wrdata_en <= d_dfi_wrdata_en_p1;
r2_dfi_wrdata_en <= r_dfi_wrdata_en;
end
assign drive_dqs = r2_dfi_wrdata_en;
assign drive_dq = d_dfi_wrdata_en_p1;
wire rddata_valid;
reg [4:0] rddata_sr;