litesdcard: use new Block2Mem/Mem2Block DMAs.

This commit is contained in:
Florent Kermarrec 2020-07-07 09:24:08 +02:00
parent eeea30eada
commit 8d76509032
2 changed files with 23 additions and 27 deletions

View file

@ -1248,7 +1248,7 @@ class LiteXSoC(SoC):
# Imports
from litesdcard.phy import SDPHY
from litesdcard.core import SDCore
from litex.soc.cores.dma import WishboneDMAWriter, WishboneDMAReader
from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
# Emulator / Pads
if with_emulator:
@ -1266,20 +1266,16 @@ class LiteXSoC(SoC):
self.add_csr("sdphy")
self.add_csr("sdcore")
# SD Card Data Reader
sdreader_bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sdreader = WishboneDMAWriter(sdreader_bus, with_csr=True, endianness=self.cpu.endianness)
self.bus.add_master("sdreader", master=sdreader_bus)
self.add_csr("sdreader")
self.submodules.sdreader_fifo = stream.SyncFIFO([("data", self.bus.data_width)], 512//(self.bus.data_width//8))
self.comb += self.sdcore.source.connect(self.sdreader_fifo.sink)
self.comb += self.sdreader_fifo.source.connect(self.sdreader.sink)
# Block2Mem DMA
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
self.bus.add_master("sdblock2mem", master=bus)
self.add_csr("sdblock2mem")
# SD Card Data Writer
sdwriter_bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sdwriter = WishboneDMAReader(sdwriter_bus, with_csr=True, endianness=self.cpu.endianness)
self.bus.add_master("sdwriter", master=sdwriter_bus)
self.add_csr("sdwriter")
self.submodules.sdwriter_fifo = stream.SyncFIFO([("data", self.bus.data_width)], 512//(self.bus.data_width//8))
self.comb += self.sdwriter.source.connect(self.sdwriter_fifo.sink)
self.comb += self.sdwriter_fifo.source.connect(self.sdcore.sink)
# Mem2Block DMA
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
self.bus.add_master("sdmem2block", master=bus)
self.add_csr("sdmem2block")

View file

@ -521,10 +521,10 @@ int sdcard_init(void) {
void sdcard_read(uint32_t sector, uint32_t count, uint8_t* buf)
{
/* Initialize DMA Writer */
sdreader_enable_write(0);
sdreader_base_write((uint32_t) buf);
sdreader_length_write(512*count);
sdreader_enable_write(1);
sdblock2mem_dma_enable_write(0);
sdblock2mem_dma_base_write((uint32_t) buf);
sdblock2mem_dma_length_write(512*count);
sdblock2mem_dma_enable_write(1);
/* Read Block(s) from SDCard */
#ifdef SDCARD_CMD23_SUPPORT
@ -533,7 +533,7 @@ sdcard_set_block_count(count);
sdcard_read_multiple_block(sector, count);
/* Wait for DMA Writer to complete */
while ((sdreader_done_read() & 0x1) == 0);
while ((sdblock2mem_dma_done_read() & 0x1) == 0);
sdcard_stop_transmission();
@ -544,13 +544,13 @@ void sdcard_write(uint32_t sector, uint32_t count, uint8_t* buf)
{
while (count--) {
/* Initialize DMA Reader */
sdwriter_enable_write(0);
sdwriter_base_write((uint32_t) buf);
sdwriter_length_write(512);
sdwriter_enable_write(1);
sdmem2block_dma_enable_write(0);
sdmem2block_dma_base_write((uint32_t) buf);
sdmem2block_dma_length_write(512);
sdmem2block_dma_enable_write(1);
/* Wait for DMA Reader to complete */
while ((sdwriter_done_read() & 0x1) == 0);
while ((sdmem2block_dma_done_read() & 0x1) == 0);
/* Write Single Block to SDCard */
#ifndef SDCARD_CMD23_SUPPORT