arp: add skeleton
This commit is contained in:
Florent Kermarrec
parent
dcbfdcab44
commit
8d9357d85f
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@ -4,21 +4,22 @@ from liteeth.generic.dispatcher import Dispatcher
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from liteeth.mac import LiteEthMAC
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class LiteEthIPStack(Module, AutoCSR):
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def __init__(self, phy):
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def __init__(self, phy,
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mac_address= 0x12345678abcd,
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ip_address="192.168.0.10"):
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self.phy = phy
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self.submodules.mac = mac = LiteEthMAC(phy, 8, interface="mac", with_hw_preamble_crc=True)
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self.submodules.arp = arp = LiteEthARP()
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self.submodules.arp = arp = LiteEthARP(mac_address, ip_address)
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self.submodules.ip = ip = LiteEthMACIP()
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# MAC dispatch
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self.submodules.mac_dispatcher = mac_dispatcher = Dispatcher(mac.source, [arp.sink, ip.sink], one_hot=True)
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self.comb += [
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If(mac.source.eth_type == ethernet_type_arp,
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mac_dispatcher.sel.eq(1)
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).Elif(mac.source.eth_type == ethernet_type_ip,
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mac_dispatcher.sel.eq(2)
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)
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]
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self.comb += \
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Case(mac.source.eth_type, {
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ethernet_type_arp : [mac_dispatcher.sel.eq(1)],
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ethernet_type_ip : [mac_dispatcher.sel.eq(2)],
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"default" : [mac_dispatcher.sel.eq(0)],
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})
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# MAC arbitrate
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self.submodules.mac_arbiter = mac_arbiter = Arbiter([arp.source, ip.source], mac.sink)
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@ -2,6 +2,15 @@ from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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def _arp_table_description():
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layout = [
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("reply", 1),
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("request", 1),
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("ip_address", 32),
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("mac_address", 48)
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]
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return EndpointDescription(layout, packetized=False)
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class LiteEthARPDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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@ -17,3 +26,183 @@ class LiteEthARPPacketizer(LiteEthDepacketizer):
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eth_mac_description(8),
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arp_header,
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arp_header_length)
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class LiteSATACommandTX(Module):
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def __init__(self, transport):
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self.sink = sink = Sink(command_tx_description(32))
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class LiteEthARPTX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = sink = Sink(_arp_table_description())
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self.source = Source(eth_mac_description(8))
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###
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packetiser = LiteEthARPPacketizer()
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self.submodules += packetizer
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source = packetizer.sink
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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NextState("SEND")
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)
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)
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self.comb += [
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source.hardware_type.eq(arp_hwtype_ethernet),
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source.protocol_type.eq(arp_proto_ip),
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source.hardware_address_length.eq(6),
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source.protocol_address_length.eq(4),
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source.source_mac_address.eq(mac_address),
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source.source_ip_address.eq(ip_address),
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If(sink.reply,
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source.operation.eq(arp_opcode_reply),
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source.destination_mac_address.eq(sink.mac_address),
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source.destination_ip_address.eq(sink.ip_address)
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).Elif(sink.request,
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source.operation.eq(arp_opcode_request),
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source.destination_mac_address.eq(0xffffffffffff),
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source.destination_ip_address.eq(sink.ip_address)
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)
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]
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fsm.act("SEND_REQUEST",
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source.stb.eq(1),
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Record.connect(packetizer.source, self.source),
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If(self.source.stb & self.source.eop & self.source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthARPRX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = Sink(eth_mac_description(8))
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self.source = source = Source(_arp_table_description())
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###
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depacketiser = LiteEthARPDepacketizer()
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self.submodules += depacketizer
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self.comb += Record.connect(self.sink, depacketizer.sink)
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sink = depacketizer.source
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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NextState("CHECK")
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)
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)
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valid = Signal()
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self.comb += valid.eq(
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sink.stb &
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(sink.hardware_type == arp_hwtype_ethernet) &
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(sink.protocol_type == arp_proto_ip) &
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(sink.hardware_address_length == 6) &
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(sink.protocol_address_length == 4) &
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(sink.destination_ip_address == ip_address)
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)
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reply = Signal()
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request = Signal()
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self.comb += Case(sink.operation, {
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arp_opcode_request : [request.eq(1)],
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arp_opcode_reply : [reply.eq(1)],
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"default" : []
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})
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self.comb += [
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source.ip_address.eq(sink.source_ip_address),
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source.mac_address.eq(sink.source_mac_address)
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]
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fsm.act("CHECK",
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If(valid,
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source.stb.eq(1),
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source.reply.eq(reply),
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source.request.eq(request)
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),
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NextState.eq("TERMINATE")
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),
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fsm.act("TERMINATE",
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sink.ack.eq(1),
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If(sink.stb & sink.source.eop & sink.source.ack,
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NextState("IDLE")
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)
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)
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arp_table_request_layout = [
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("ip_address", 32)
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]
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arp_table_response_layout = [
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("failed", 1),
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("mac_address", 48)
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]
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class LiteEthARPTable(Module):
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def __init__(self):
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self.sink = sink = Sink(_arp_table_description()) # from arp_rx
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self.source = source = Source(_arp_table_description()) # to arp_tx
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# Request/Response interface
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self.request = request = Sink(arp_table_request_layout)
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self.response = response = Source(arp_table_response_layout)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(sink.stb & sink.request,
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NextState("SEND_REPLY")
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).Elif(sink.stb & sink.reply,
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NextState("UPDATE_TABLE")
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).Elif(request.stb,
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NextState("CHECK_TABLE")
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)
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)
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fsm.act("SEND_REPLY",
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source.stb.eq(1),
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source.reply.eq(1),
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source.ip_address.eq(sink.ip_address),
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If(source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("UPDATE_TABLE",
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# XXX update memory
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NextState("IDLE")
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)
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found = Signal()
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fsm.act("CHECK_TABLE",
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# XXX add a kind of CAM?
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If(found,
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NexState.eq("PRESENT_RESPONSE")
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).Else(
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NextState.eq("SEND_REQUEST")
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)
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)
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fsm.act("SEND_REQUEST",
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source.stb.eq(1),
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source.request.eq(1),
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source.ip_address.eq(request.ip_address),
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If(source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("PRESENT_RESPONSE",
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response.stb.eq(1),
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response.failed.eq(0), # XXX add timeout to trigger failed
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response.mac_address.eq(0x12345678abcd), # XXX get mac address from table
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If(response.ack,
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NextState("IDLE")
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)
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)
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class LiteEthARP(Module):
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def __init__(self, mac_address, ip_address):
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self.submodules.tx = LiteEthARPTX(mac_address, ip_address)
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self.submodules.rx = LiteEthARPRX(mac_address, ip_address)
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self.submodules.table = LiteEthARPTable()
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self.comb += [
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Record.connect(self.rx.source, self.table.sink),
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Record.connect(self.table.source, self.tx.sink)
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]
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self.sink, self.source = self.rx.sink, self.tx.source
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self.request, self.response = self.table.request, self.table.response
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