x.bv.width -> len(x)

migen/bus/wishbone.py

@@ -90,8 +90,8 @@ class Decoder:
 		slave_sel_r = Signal(BV(ns))
 		
 		# decode slave addresses
-		hi = self.master.adr.bv.width - self.offset
-		comb += [slave_sel[i].eq(self.master.adr[hi-addr.bv.width:hi] == addr)
+		hi = len(self.master.adr) - self.offset
+		comb += [slave_sel[i].eq(self.master.adr[hi-len(addr):hi] == addr)
 			for i, addr in enumerate(self.addresses)]
 		if self.register:
 			sync.append(slave_sel_r.eq(slave_sel))
@@ -114,7 +114,7 @@ class Decoder:
 		]
 		
 		# mux (1-hot) slave data return
-		masked = [Replicate(slave_sel_r[i], self.master.dat_r.bv.width) & self.slaves[i][1].dat_r for i in range(len(self.slaves))]
+		masked = [Replicate(slave_sel_r[i], len(self.master.dat_r)) & self.slaves[i][1].dat_r for i in range(len(self.slaves))]
 		comb.append(self.master.dat_r.eq(optree("|", masked)))
 		
 		return Fragment(comb, sync)

migen/corelogic/misc.py

@@ -30,8 +30,8 @@ def split(v, *counts):
 
 def displacer(signal, shift, output, n=None, reverse=False):
 	if n is None:
-		n = 2**shift.bv.width
-	w = signal.bv.width
+		n = 2**len(shift)
+	w = len(signal)
 	if reverse:
 		r = reversed(range(n))
 	else:
@@ -41,8 +41,8 @@ def displacer(signal, shift, output, n=None, reverse=False):
 
 def chooser(signal, shift, output, n=None, reverse=False):
 	if n is None:
-		n = 2**shift.bv.width
-	w = output.bv.width
+		n = 2**len(shift)
+	w = len(output)
 	cases = []
 	for i in range(n):
 		if reverse:

migen/corelogic/record.py

@@ -87,7 +87,7 @@ class Record:
 			else:
 				raise TypeError
 			for x in added:
-				offset += x.bv.width
+				offset += len(x)
 			l += added
 		if return_offset:
 			return (l, offset)

migen/fhdl/structure.py

@@ -17,7 +17,7 @@ def log2_int(n):
 
 def bits_for(n):
 	if isinstance(n, Constant):
-		return n.bv.width
+		return len(n)
 	else:
 		if n < 0:
 			return bits_for(-n) + 1
@@ -97,9 +97,9 @@ class Value:
 			return _Slice(self, key, key+1)
 		elif isinstance(key, slice):
 			start = key.start or 0
-			stop = key.stop or self.bv.width
-			if stop > self.bv.width:
-				stop = self.bv.width
+			stop = key.stop or len(self)
+			if stop > len(self):
+				stop = len(self)
 			if key.step != None:
 				raise KeyError
 			return _Slice(self, start, stop)

migen/fhdl/verilog.py

@@ -11,8 +11,8 @@ def _printsig(ns, s):
 		n = "signed "
 	else:
 		n = ""
-	if s.bv.width > 1:
-		n += "[" + str(s.bv.width-1) + ":0] "
+	if len(s) > 1:
+		n += "[" + str(len(s)-1) + ":0] "
 	n += ns.get_name(s)
 	return n
 
@@ -36,7 +36,7 @@ def _printexpr(ns, node):
 	elif isinstance(node, _Slice):
 		# Verilog does not like us slicing non-array signals...
 		if isinstance(node.value, Signal) \
-		  and node.value.bv.width == 1 \
+		  and len(node.value) == 1 \
 		  and node.start == 0 and node.stop == 1:
 			  return _printexpr(ns, node.value)
 

migen/sim/generic.py

@@ -121,7 +121,7 @@ class Simulator:
 			nbits = item.width
 		else:
 			signed = item.bv.signed
-			nbits = item.bv.width
+			nbits = len(item)
 		value = reply.value & (2**nbits - 1)
 		if signed and (value & 2**(nbits - 1)):
 			value -= 2**nbits
@@ -134,7 +134,7 @@ class Simulator:
 		if isinstance(item, Memory):
 			nbits = item.width
 		else:
-			nbits = item.bv.width
+			nbits = len(item)
 		if value < 0:
 			value += 2**nbits
 		assert(value >= 0 and value < 2**nbits)