pipistrello: use fpgaprog
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@ -1,7 +1,7 @@
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from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.xilinx.ise import XilinxISEPlatform
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from mibuild.xilinx.programmer import XC3SProg
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from mibuild.xilinx.programmer import FpgaProg
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_io = [
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("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green near hdmi
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@ -119,7 +119,7 @@ class Platform(XilinxISEPlatform):
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lambda p: SimpleCRG(p, "clk50", None), _connectors)
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def create_programmer(self):
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return XC3SProg("ftdi", "bscan_spi_lx45_csg324.bit")
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return FpgaProg("bscan_spi_lx45_csg324.bit")
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def do_finalize(self, fragment):
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try:
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