memtest/LFSR: use module decorators

This commit is contained in:
Sebastien Bourdeauducq 2013-07-25 17:57:17 +02:00
parent 764e7c07e4
commit 8e04de524b
1 changed files with 7 additions and 10 deletions

View File

@ -4,10 +4,10 @@ from migen.bank.description import *
from migen.actorlib import dma_lasmi from migen.actorlib import dma_lasmi
from migen.actorlib.spi import * from migen.actorlib.spi import *
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class LFSR(Module): class LFSR(Module):
def __init__(self, n_out, n_state=31, taps=[27, 30]): def __init__(self, n_out, n_state=31, taps=[27, 30]):
self.ce = Signal()
self.reset = Signal()
self.o = Signal(n_out) self.o = Signal(n_out)
### ###
@ -20,18 +20,15 @@ class LFSR(Module):
curval.insert(0, nv) curval.insert(0, nv)
curval.pop() curval.pop()
self.sync += If(self.reset, self.sync += [
state.eq(0), state.eq(Cat(*curval[:n_state])),
self.o.eq(0) self.o.eq(Cat(*curval))
).Elif(self.ce, ]
state.eq(Cat(*curval[:n_state])),
self.o.eq(Cat(*curval))
)
def _print_lfsr_code(): def _print_lfsr_code():
from migen.fhdl import verilog from migen.fhdl import verilog
dut = LFSR(3, 4, [3, 2]) dut = LFSR(3, 4, [3, 2])
print(verilog.convert(dut, ios={dut.ce, dut.o})) print(verilog.convert(dut, ios={dut.ce, dut.reset, dut.o}))
class _LFSRTB(Module): class _LFSRTB(Module):
def __init__(self, *args, **kwargs): def __init__(self, *args, **kwargs):