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bus/csr/SRAM: fix Module conversion errors

This commit is contained in:
Sebastien Bourdeauducq 2013-04-14 13:55:04 +02:00
parent ea63389823
commit 8e11fcf1d0
1 changed files with 3 additions and 3 deletions
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6
migen/bus/csr.py
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@ -61,14 +61,14 @@ class SRAM(Module):
else:
mem = Memory(data_width, mem_or_size//(data_width//8))
if mem.width > data_width:
csrw_per_memw = (self.mem.width + data_width - 1)//data_width
csrw_per_memw = (mem.width + data_width - 1)//data_width
word_bits = bits_for(csrw_per_memw-1)
else:
csrw_per_memw = 1
word_bits = 0
page_bits = _compute_page_bits(mem.depth + word_bits)
if page_bits:
self._page = CSRStorage(page_bits, name=self.mem.name_override + "_page")
self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
else:
self._page = None
if read_only is None:
@ -94,7 +94,7 @@ class SRAM(Module):
if word_bits:
word_index = Signal(word_bits)
word_expanded = Signal(csrw_per_memw*data_width)
sync.append(word_index.eq(self.bus.adr[:word_bits]))
self.sync += word_index.eq(self.bus.adr[:word_bits])
self.comb += [
word_expanded.eq(port.dat_r),
If(sel_r,