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targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).

This commit is contained in:
Florent Kermarrec 2020-02-28 09:48:48 +01:00
parent a7c5dd5d3e
commit 8e1d528663
2 changed files with 13 additions and 11 deletions
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14
litex/boards/targets/ulx3s.py
View File

@ -12,6 +12,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import ulx3s
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
@ -50,7 +52,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, device="LFE5U-45F", toolchain="diamond",
def __init__(self, device="LFE5U-45F", toolchain="trellis",
sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
@ -72,16 +74,17 @@ class BaseSoC(SoCSDRAM):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help="gateware toolchain to use, trellis (default) or diamond")
parser.add_argument("--device", dest="device", default="LFE5U-45F",
help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F')
help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
parser.add_argument("--sys-clk-freq", default=50e6,
help="system clock frequency (default=50MHz)")
parser.add_argument("--sdram-module", default="MT48LC16M16",
help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(device=args.device, toolchain=args.toolchain,
@ -89,7 +92,8 @@ def main():
sdram_module_cls=args.sdram_module,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
if __name__ == "__main__":
main()

10
litex/boards/targets/versa_ecp5.py
View File

@ -102,7 +102,7 @@ class EthernetSoC(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, toolchain="diamond", **kwargs):
def __init__(self, toolchain="trellis", **kwargs):
BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
@ -130,8 +130,8 @@ class EthernetSoC(BaseSoC):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help="gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
@ -144,9 +144,7 @@ def main():
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = {}
if args.toolchain == "trellis":
builder_kargs == trellis_argdict(args)
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
if __name__ == "__main__":