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spiflash: style

This commit is contained in:
Sebastien Bourdeauducq 2015-03-03 00:54:30 +00:00
parent 2513833a24
commit 8e48502d03
1 changed files with 2 additions and 2 deletions
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4
misoclib/mem/flash/spiflash/__init__.py
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@ -30,7 +30,7 @@ class SpiFlash(Module, AutoCSR):
Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
Read). Only supports mode0 (cpol=0, cpha=0).
Optional supports software bitbanging (for write, erase, or other commands).
Optionally supports software bitbanging (for write, erase, or other commands).
"""
self.bus = bus = wishbone.Interface()
spi_width = flen(pads.dq)
@ -39,7 +39,7 @@ class SpiFlash(Module, AutoCSR):
self.miso = CSRStatus()
self.bitbang_en = CSRStorage()
##
###
cs_n = Signal(reset=1)
clk = Signal()