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use new direct access on endpoints

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This commit is contained in:
Florent Kermarrec 2014-10-20 23:13:33 +08:00 committed by Sebastien Bourdeauducq
parent 34ed315a48
commit 8e4b89849c
3 changed files with 11 additions and 11 deletions
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10
misoclib/framebuffer/format.py
View file

@ -91,7 +91,7 @@ class VTG(Module):
If(active,
[getattr(getattr(self.phy.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
for p in ["p"+str(i) for i in range(pack_factor)] for c in ["r", "g", "b"]],
self.phy.payload.de.eq(1)
self.phy.de.eq(1)
),
self.pixels.ack.eq(self.phy.ack & active)
]
@ -109,8 +109,8 @@ class VTG(Module):
If(hcounter == 0, hactive.eq(1)),
If(hcounter == tr.hres, hactive.eq(0)),
If(hcounter == tr.hsync_start, self.phy.payload.hsync.eq(1)),
If(hcounter == tr.hsync_end, self.phy.payload.hsync.eq(0)),
If(hcounter == tr.hsync_start, self.phy.hsync.eq(1)),
If(hcounter == tr.hsync_end, self.phy.hsync.eq(0)),
If(hcounter == tr.hscan,
hcounter.eq(0),
If(vcounter == tr.vscan,
@ -123,8 +123,8 @@ class VTG(Module):
If(vcounter == 0, vactive.eq(1)),
If(vcounter == tr.vres, vactive.eq(0)),
If(vcounter == tr.vsync_start, self.phy.payload.vsync.eq(1)),
If(vcounter == tr.vsync_end, self.phy.payload.vsync.eq(0))
If(vcounter == tr.vsync_start, self.phy.vsync.eq(1)),
If(vcounter == tr.vsync_end, self.phy.vsync.eq(0))
)
]

4
misoclib/memtest/__init__.py
View file

@ -57,7 +57,7 @@ class MemtestWriter(Module):
self._dma.trigger.eq(self._r_shoot.re),
self._dma.data.stb.eq(en),
lfsr.ce.eq(en & self._dma.data.ack),
self._dma.data.payload.d.eq(lfsr.o)
self._dma.data.d.eq(lfsr.o)
]
def get_csrs(self):
@ -87,7 +87,7 @@ class MemtestReader(Module):
If(self._r_reset.re,
err_cnt.eq(0)
).Elif(self._dma.data.stb,
If(self._dma.data.payload.d != lfsr.o, err_cnt.eq(err_cnt + 1))
If(self._dma.data.d != lfsr.o, err_cnt.eq(err_cnt + 1))
)
]

8
misoclib/uart/__init__.py
View file

@ -21,7 +21,7 @@ class UARTRX(Module):
rx_bitcount = Signal(4)
rx_busy = Signal()
rx_done = self.source.stb
rx_data = self.source.payload.d
rx_data = self.source.d
self.sync += [
rx_done.eq(0),
rx_r.eq(rx),
@ -73,7 +73,7 @@ class UARTTX(Module):
self.sync += [
self.sink.ack.eq(0),
If(self.sink.stb & ~tx_busy & ~self.sink.ack,
tx_reg.eq(self.sink.payload.d),
tx_reg.eq(self.sink.d),
tx_bitcount.eq(0),
tx_busy.eq(1),
pads.tx.eq(0)
@ -120,12 +120,12 @@ class UART(Module, AutoCSR):
self.sync += [
If(self._r_rxtx.re,
self.tx.sink.stb.eq(1),
self.tx.sink.payload.d.eq(self._r_rxtx.r),
self.tx.sink.d.eq(self._r_rxtx.r),
).Elif(self.tx.sink.ack,
self.tx.sink.stb.eq(0)
),
If(self.rx.source.stb,
self._r_rxtx.w.eq(self.rx.source.payload.d)
self._r_rxtx.w.eq(self.rx.source.d)
)
]
self.comb += [