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soc/integration/soc_core: instanciate wishbone/csr/interrupts only if we have at least a wishbone master

This commit is contained in:
Florent Kermarrec 2016-02-10 10:23:42 +01:00
parent 34b45e3618
commit 8ee3874088
1 changed files with 19 additions and 18 deletions
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litex/soc/integration/soc_core.py
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@ -179,6 +179,7 @@ class SoCCore(Module):
if mem not in registered_mems: if mem not in registered_mems:
raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem)) raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
if len(self._wb_masters):
# Wishbone # Wishbone
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
self._wb_slaves, register=True) self._wb_slaves, register=True)