soc/integration/soc_core: instanciate wishbone/csr/interrupts only if we have at least a wishbone master

litex/soc/integration/soc_core.py

@@ -179,6 +179,7 @@ class SoCCore(Module):
                 if mem not in registered_mems:
                     raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
 
+        if len(self._wb_masters):
             # Wishbone
             self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
                 self._wb_slaves, register=True)