soc/interconnect/wishbone: Add incrementing burst cycles support to SRAM
This commit adds support for incrementing burst cycles in SRAM peripheral. By default it's enabled, but can be disabled by passing `burst=False` to the class while initializing, if it won't be useful for created design (e.g. no Wishbone bus masters with burst support).
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@ -4,6 +4,7 @@
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# Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
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# Copytight (c) 2022 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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"""Wishbone Classic support for LiteX (Standard HandShaking/Synchronous Feedback)"""
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@ -329,7 +330,7 @@ class Converter(Module):
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# Wishbone SRAM ------------------------------------------------------------------------------------
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class SRAM(Module):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=True):
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if bus is None:
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bus = Interface()
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self.bus = bus
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@ -346,6 +347,79 @@ class SRAM(Module):
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else:
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read_only = False
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###
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if burst:
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adr_wrap_mask = Array((0b0000, 0b0011, 0b0111, 0b1111))
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adr_wrap_max = adr_wrap_mask[-1].bit_length()
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adr_burst_wrap = Signal()
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adr_burst_end = Signal()
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adr_burst = Signal()
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adr_latched = Signal()
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adr_counter = Signal(len(self.bus.adr))
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adr_counter_offset = Signal(adr_wrap_max)
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adr_offset_lsb = Signal(adr_wrap_max)
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adr_offset_msb = Signal(len(self.bus.adr))
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adr_next = Signal(len(self.bus.adr))
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# only incrementing burst cycles are supported
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self.comb += [
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Case(self.bus.cti, {
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# incrementing address burst cycle
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0b010: adr_burst.eq(1),
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# end current burst cycle
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0b111: adr_burst.eq(0),
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# unsupported burst cycle
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"default": adr_burst.eq(0)
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}),
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adr_burst_wrap.eq(self.bus.bte[0] | self.bus.bte[1])
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]
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# latch initial address - initial address without wrapping bits and wrap offset
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self.sync += [
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If(self.bus.cyc & self.bus.stb & adr_burst,
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adr_latched.eq(1),
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# latch initial address, then increment it every clock cycle
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If(adr_latched,
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adr_counter.eq(adr_counter + 1)
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).Else(
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adr_counter_offset.eq(self.bus.adr & adr_wrap_mask[self.bus.bte]),
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If(self.bus.we,
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adr_counter.eq(
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Cat(self.bus.adr & ~adr_wrap_mask[self.bus.bte],
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self.bus.adr[adr_wrap_max:]
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)
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),
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).Else(
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adr_counter.eq(
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Cat(self.bus.adr & ~adr_wrap_mask[self.bus.bte],
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self.bus.adr[adr_wrap_max:]
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) + 1
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),
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)
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),
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If(self.bus.cti == 0b111,
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adr_latched.eq(0),
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adr_counter.eq(0),
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adr_counter_offset.eq(0)
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)
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).Else(
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adr_latched.eq(0),
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adr_counter.eq(0),
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adr_counter_offset.eq(0)
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),
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]
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# next address = sum of counter value without wrapped bits
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# and wrapped counter bits with offset
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self.comb += [
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adr_offset_lsb.eq((adr_counter + adr_counter_offset) & adr_wrap_mask[self.bus.bte]),
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adr_offset_msb.eq(adr_counter & ~adr_wrap_mask[self.bus.bte]),
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adr_next.eq(adr_offset_msb + adr_offset_lsb)
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]
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###
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# memory
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@ -357,15 +431,34 @@ class SRAM(Module):
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self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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for i in range(bus_data_width//8)]
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# address and data
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if burst:
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self.comb += [
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If(adr_burst & adr_latched,
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port.adr.eq(adr_next[:len(port.adr)]),
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).Else(
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port.adr.eq(self.bus.adr[:len(port.adr)]),
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),
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]
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else:
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self.comb += [
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port.adr.eq(self.bus.adr[:len(port.adr)]),
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]
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self.comb += [
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self.bus.dat_r.eq(port.dat_r)
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]
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if not read_only:
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self.comb += port.dat_w.eq(self.bus.dat_w),
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# generate ack
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self.sync += [
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self.bus.ack.eq(0),
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self.bus.ack.eq(0)
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]
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if burst:
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self.sync += [
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If(self.bus.cyc & self.bus.stb & (~self.bus.ack | adr_burst), self.bus.ack.eq(1))
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]
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else:
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self.sync += [
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
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]
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